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Small bug fixes related to new name mapping.

This commit is contained in:
mrg 2020-11-16 13:42:42 -08:00
parent 1d729e8f02
commit 86799ae3ff
11 changed files with 68 additions and 71 deletions
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27
compiler/base/custom_cell_properties.py
View File

@ -46,7 +46,7 @@ class _cell:
def port_order(self, x):
self._port_order = x
# Update ordered name list in the new order
self._port_names = [getattr(self._pins, x) for x in self._port_order]
self._port_names = [self._port_map[x] for x in self._port_order]
# Update ordered type list in the new order
self._port_types = [self._port_types_map[x] for x in self._port_order]
@ -57,9 +57,8 @@ class _cell:
@port_map.setter
def port_map(self, x):
self._port_map = x
self._pins = _pins(x)
# Update ordered name list to use the new names
self._port_names = [getattr(self._pins, x) for x in self._port_order]
self._port_names = [self.port_map[x] for x in self._port_order]
@property
def port_types(self):
@ -153,10 +152,6 @@ class cell_properties():
self._dff = _cell(["D", "Q", "clk", "vdd", "gnd"],
["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
self._dff_buf = _cell(["D", "Q", "Qb", "clk", "vdd", "gnd"],
["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"],
hard_cell=False)
self._write_driver = _cell(['din', 'bl', 'br', 'en', 'vdd', 'gnd'],
["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
@ -169,6 +164,12 @@ class cell_properties():
self._bitcell_2port = _bitcell(["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"],
["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"])
self._col_cap_2port = _bitcell(["bl0", "br0", "bl1", "br1", "vdd"],
["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "POWER"])
self._row_cap_2port = _bitcell(["wl0", "wl1", "gnd"],
["INPUT", "INPUT", "POWER", "GROUND"])
@property
def ptx(self):
return self._ptx
@ -197,10 +198,6 @@ class cell_properties():
def dff(self):
return self._dff
@property
def dff_buf(self):
return self._dff_buf
@property
def write_driver(self):
return self._write_driver
@ -217,3 +214,11 @@ class cell_properties():
def bitcell_2port(self):
return self._bitcell_2port
@property
def col_cap_2port(self):
return self._col_cap_2port
@property
def row_cap_2port(self):
return self._row_cap_2port

48
compiler/base/geometry.py
View File

@ -275,16 +275,16 @@ class instance(geometry):
def calculate_transform(self, node):
#set up the rotation matrix
angle = math.radians(float(node.rotate))
mRotate = np.array([[math.cos(angle),-math.sin(angle),0.0],
[math.sin(angle),math.cos(angle),0.0],
[0.0,0.0,1.0]])
mRotate = np.array([[math.cos(angle), -math.sin(angle), 0.0],
[math.sin(angle), math.cos(angle), 0.0],
[0.0, 0.0, 1.0]])
#set up translation matrix
translateX = float(node.offset[0])
translateY = float(node.offset[1])
mTranslate = np.array([[1.0,0.0,translateX],
[0.0,1.0,translateY],
[0.0,0.0,1.0]])
mTranslate = np.array([[1.0, 0.0, translateX],
[0.0, 1.0, translateY],
[0.0, 0.0, 1.0]])
#set up the scale matrix (handles mirror X)
scaleX = 1.0
@ -292,27 +292,27 @@ class instance(geometry):
scaleY = -1.0
else:
scaleY = 1.0
mScale = np.array([[scaleX,0.0,0.0],
[0.0,scaleY,0.0],
[0.0,0.0,1.0]])
mScale = np.array([[scaleX, 0.0, 0.0],
[0.0, scaleY, 0.0],
[0.0, 0.0, 1.0]])
return (mRotate, mScale, mTranslate)
def apply_transform(self, mtransforms, uVector, vVector, origin):
origin = np.dot(mtransforms[0], origin) #rotate
uVector = np.dot(mtransforms[0], uVector) #rotate
vVector = np.dot(mtransforms[0], vVector) #rotate
origin = np.dot(mtransforms[1], origin) #scale
uVector = np.dot(mtransforms[1], uVector) #scale
vVector = np.dot(mtransforms[1], vVector) #scale
origin = np.dot(mtransforms[0], origin) # rotate
uVector = np.dot(mtransforms[0], uVector) # rotate
vVector = np.dot(mtransforms[0], vVector) # rotate
origin = np.dot(mtransforms[1], origin) # scale
uVector = np.dot(mtransforms[1], uVector) # scale
vVector = np.dot(mtransforms[1], vVector) # scale
origin = np.dot(mtransforms[2], origin)
return(uVector, vVector, origin)
def apply_path_transform(self, path):
uVector = np.array([[1.0],[0.0],[0.0]])
vVector = np.array([[0.0],[1.0],[0.0]])
origin = np.array([[0.0],[0.0],[1.0]])
uVector = np.array([[1.0], [0.0], [0.0]])
vVector = np.array([[0.0], [1.0], [0.0]])
origin = np.array([[0.0], [0.0], [1.0]])
while(path):
instance = path.pop(-1)
@ -330,7 +330,7 @@ class instance(geometry):
bl_offsets = [] # bl to cell offset
br_offsets = [] # br to cell offset
bl_meta = [] # bl offset metadata (row,col,name)
br_meta = [] #br offset metadata (row,col,name)
br_meta = [] # br offset metadata (row,col,name)
def walk_subtree(node):
path.append(node)
@ -338,8 +338,6 @@ class instance(geometry):
if node.mod.name == cell_name:
cell_paths.append(copy.copy(path))
inst_name = path[-1].name
# get the row and col names from the path
row = int(path[-1].name.split('_')[-2][1:])
col = int(path[-1].name.split('_')[-1][1:])
@ -370,17 +368,15 @@ class instance(geometry):
for pair in range(len(normalized_bl_offsets)):
normalized_bl_offsets[pair] = (normalized_bl_offsets[pair][0],
-1 * normalized_bl_offsets[pair][1])
-1 * normalized_bl_offsets[pair][1])
for pair in range(len(normalized_br_offsets)):
normalized_br_offsets[pair] = (normalized_br_offsets[pair][0],
-1 * normalized_br_offsets[pair][1])
-1 * normalized_br_offsets[pair][1])
Q_offsets.append([Q_x, Q_y])
Q_bar_offsets.append([Q_bar_x, Q_bar_y])
bl_offsets.append(normalized_bl_offsets)
br_offsets.append(normalized_br_offsets)
@ -428,7 +424,7 @@ class path(geometry):
def gds_write_file(self, new_layout):
"""Writes the path to GDS"""
debug.info(4, "writing path (" + str(self.layerNumber) + "): " + self.coordinates)
debug.info(4, "writing path (" + str(self.layerNumber) + "): " + self.coordinates)
new_layout.addPath(layerNumber=self.layerNumber,
purposeNumber=self.layerPurpose,
coordinates=self.coordinates,

2
compiler/base/hierarchy_layout.py
View File

@ -373,7 +373,7 @@ class layout():
for pin in pins:
if new_name == "":
new_name = pin.name
new_name = pin_name
self.add_layout_pin(new_name,
pin.layer,
pin.ll(),

3
compiler/base/hierarchy_spice.py
View File

@ -239,7 +239,8 @@ class spice():
subckt_line = list(filter(subckt.search, self.lvs))[0]
# parses line into ports and remove subckt
lvs_pins = subckt_line.split(" ")[2:]
debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.")
debug.check(lvs_pins == self.pins,
"Spice netlists for LVS and simulation have port mismatches: {0} (LVS) vs {1} (sim)".format(lvs_pins, self.pins))
def check_net_in_spice(self, net_name):
"""Checks if a net name exists in the current. Intended to be check nets in hand-made cells."""

9
compiler/bitcells/bitcell_2port.py
View File

@ -94,9 +94,8 @@ class bitcell_2port(bitcell_base.bitcell_base):
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
# Edges hardcoded here. Essentially wl->bl/br for both ports.
# Port 0 edges
pins = props.bitcell_2port.pin
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self)
# Port 1 edges
graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)

4
compiler/bitcells/col_cap_bitcell_2port.py
View File

@ -15,8 +15,8 @@ class col_cap_bitcell_2port(bitcell_base.bitcell_base):
Column end cap cell.
"""
def __init__(self, name="col_cap_cell_1rw_1r"):
bitcell_base.bitcell_base.__init__(self, name, prop=props.bitcell_2port)
def __init__(self, name="col_cap_bitcell_2port"):
bitcell_base.bitcell_base.__init__(self, name, prop=props.col_cap_2port)
debug.info(2, "Create col_cap bitcell 2 port object")
self.no_instances = True

6
compiler/bitcells/row_cap_bitcell_2port.py
View File

@ -15,8 +15,8 @@ class row_cap_bitcell_2port(bitcell_base.bitcell_base):
Row end cap cell.
"""
def __init__(self, name="row_cap_cell_1rw_1r"):
bitcell_base.bitcell_base.__init__(self, name, prop=props.bitcell_2port)
debug.info(2, "Create row_cap bitcell 1rw+1r object")
def __init__(self, name="row_cap_bitcell_2port"):
bitcell_base.bitcell_base.__init__(self, name, prop=props.row_cap_2port)
debug.info(2, "Create row_cap bitcell 2 port object")
self.no_instances = True

15
compiler/modules/col_cap_array.py
View File

@ -6,7 +6,6 @@
from bitcell_base_array import bitcell_base_array
from sram_factory import factory
from globals import OPTS
from tech import cell_properties
class col_cap_array(bitcell_base_array):
@ -65,16 +64,14 @@ class col_cap_array(bitcell_base_array):
"""
if len(self.all_ports) == 1:
pin_name = cell_properties.bitcell.cell_6t.pin
bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
"{0}_{1}".format(pin_name.br0, col),
bitcell_pins = ["bl0_{0}".format(col),
"br0_{0}".format(col),
"vdd"]
else:
pin_name = cell_properties.bitcell.cell_1rw1r.pin
bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
"{0}_{1}".format(pin_name.br0, col),
"{0}_{1}".format(pin_name.bl1, col),
"{0}_{1}".format(pin_name.br1, col),
bitcell_pins = ["bl0_{0}".format(col),
"br0_{0}".format(col),
"bl1_{0}".format(col),
"br1_{0}".format(col),
"vdd"]
return bitcell_pins

6
compiler/modules/dff_buf.py
View File

@ -8,7 +8,6 @@
import debug
import design
from tech import layer
from tech import cell_properties as props
from vector import vector
from globals import OPTS
from sram_factory import factory
@ -72,9 +71,8 @@ class dff_buf(design.design):
self.add_mod(self.inv2)
def add_pins(self):
self.add_pin_names(props.dff_buf.port_map)
self.add_pin_list(props.dff_buf.port_names,
props.dff_buf.port_types)
self.add_pin_list(["D", "Q", "Qb", "clk", "vdd", "gnd"],
["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
def create_instances(self):
self.dff_inst=self.add_inst(name="dff_buf_dff",

13
compiler/modules/replica_column.py
View File

@ -5,7 +5,6 @@
#
import debug
from bitcell_base_array import bitcell_base_array
from tech import cell_properties as props
from sram_factory import factory
from vector import vector
from globals import OPTS
@ -31,8 +30,15 @@ class replica_column(bitcell_base_array):
# left, right, regular rows plus top/bottom dummy cells
self.total_size = self.left_rbl + rows + self.right_rbl
# Used for pin names and properties
self.cell = factory.create(module_type=OPTS.bitcell)
# For end caps
self.total_size += 2
try:
if not self.cell.end_caps:
self.total_size += 2
except AttributeError:
self.total_size += 2
self.column_offset = column_offset
@ -86,9 +92,6 @@ class replica_column(bitcell_base_array):
self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell)
self.add_mod(self.edge_cell)
# Used for pin names only
self.cell = factory.create(module_type=OPTS.bitcell)
def create_instances(self):
self.cell_inst = {}

6
compiler/modules/row_cap_array.py
View File

@ -6,7 +6,6 @@
from bitcell_base_array import bitcell_base_array
from sram_factory import factory
from globals import OPTS
from tech import cell_properties
class row_cap_array(bitcell_base_array):
@ -61,9 +60,8 @@ class row_cap_array(bitcell_base_array):
indexed by column and row, for instance use in bitcell_array
"""
pin_name = cell_properties.bitcell.cell_1rw1r.pin
bitcell_pins = ["{0}_{1}".format(pin_name.wl0, row),
"{0}_{1}".format(pin_name.wl1, row),
bitcell_pins = ["wl0_{0}".format(row),
"wl1_{0}".format(row),
"gnd"]
return bitcell_pins