mirror of https://github.com/VLSIDA/OpenRAM.git
no wl for col end
This commit is contained in:
jcirimel
parent
4a1a7e637e
commit
d40c3588ed
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@ -45,8 +45,7 @@ class _bitcell:
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cell_s8_6t = _cell({'bl' : 'bl0',
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'br' : 'bl1',
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'wl0': 'wl0',
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'wl1': 'wl1'})
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'wl': 'wl'})
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cell_6t = _cell({'bl' : 'bl',
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'br' : 'br',
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@ -181,4 +180,4 @@ class cell_properties():
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if ports == "{}R_{}W_{}RW".format(OPTS.num_r_ports, OPTS.num_w_ports, OPTS.num_rw_ports):
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use_custom_arrangement = True
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break
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return use_custom_arrangement
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return use_custom_arrangement
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@ -27,11 +27,11 @@ class s8_bitcell(bitcell_base.bitcell_base):
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pin_names = ["bl0", "bl1", "wl0", "wl1", "vpwr", "vgnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
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else:
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pin_names = [props.bitcell.cell_6t.pin.bl,
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props.bitcell.cell_6t.pin.br,
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props.bitcell.cell_6t.pin.wl,
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props.bitcell.cell_6t.pin.vdd,
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props.bitcell.cell_6t.pin.gnd]
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pin_names = [props.bitcell.cell_s8_6t.pin.bl,
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props.bitcell.cell_s8_6t.pin.br,
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props.bitcell.cell_s8_6t.pin.wl,
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"vpwr",
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"vgnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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storage_nets = ['Q', 'Q_bar']
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@ -61,15 +61,12 @@ class s8_bitcell(bitcell_base.bitcell_base):
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layer["mem"],
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"s8sram_cell\x00")
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#debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells")
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def get_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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if props.compare_ports(props.bitcell.split_wl):
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row_pins = ["wl0", "wl1"]
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else:
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row_pins = [props.bitcell.s8_sp.pin.wl]
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row_pins = [props.bitcell.cell_s8_6t.pin.wl]
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return row_pins
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def get_all_bitline_names(self):
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@ -21,6 +21,7 @@ class s8_col_cap_array(design.design):
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self.column_offset = column_offset
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self.mirror = mirror
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self.no_instances = True
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self.all_wordline_names = []
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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@ -21,8 +21,8 @@ class s8_col_end(design.design):
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type_list = []
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if version == "colend":
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self.name = "s8sram16x16_colenda"
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structure = "s8sram16x16_colenda\x00"
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self.name = "s8sram16x16_colend"
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structure = "s8sram16x16_colend"
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elif version == "colend_p_cent":
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self.name = "s8sram16x16_colend_p_cent"
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structure = "s8sram16x16_colend_p_cent\x00"
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@ -24,11 +24,11 @@ class s8_dummy_bitcell(bitcell_base.bitcell_base):
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pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
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else:
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pin_names = [props.bitcell.cell_6t.pin.bl,
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props.bitcell.cell_6t.pin.br,
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props.bitcell.cell_6t.pin.wl,
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props.bitcell.cell_6t.pin.vdd,
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props.bitcell.cell_6t.pin.gnd]
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pin_names = [props.bitcell.cell_s8_6t.pin.bl,
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props.bitcell.cell_s8_6t.pin.br,
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props.bitcell.cell_s8_6t.pin.wl,
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"vpwr",
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"vgnd"]
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@ -130,10 +130,9 @@ class s8_row_cap_array(design.design):
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def add_pins(self):
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for row in range(self.rows):
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for row in range(self.rows - 2):
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for port in self.all_ports:
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self.add_pin("wl0_{}_{}".format(port, row), "OUTPUT")
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self.add_pin("wl1_{}_{}".format(port, row), "OUTPUT")
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self.add_pin("wl_{}_{}".format(port, row), "OUTPUT")
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self.add_pin("vpwr", "POWER")
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self.add_pin("vgnd", "GROUND")
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@ -56,31 +56,29 @@ class bitcell_base_array(design.design):
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# def get_all_wordline_names(self, prefix=""):
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# return [prefix + x for x in self.all_wordline_names]
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def create_all_wordline_names(self):
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for row in range(self.row_size):
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def create_all_wordline_names(self, remove_wordline = 0):
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for row in range(self.row_size - remove_wordline):
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for port in self.all_ports:
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if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
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self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
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else:
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self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
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self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
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self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
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def add_pins(self):
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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else:
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vpwr", "POWER")
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self.add_pin("vgnd", "GROUND")
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def get_bitcell_pins(self, row, col):
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""" Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array """
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@ -98,7 +98,7 @@ class dummy_array(bitcell_base_array):
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height=self.height)
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wl_names = self.cell.get_all_wl_names()
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if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
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if not props.compare_ports(props.bitcell.split_wl):
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for row in range(self.row_size):
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for port in self.all_ports:
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wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
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@ -267,96 +267,74 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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for port in self.all_ports:
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for bit in self.all_ports:
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if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
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#if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
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self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
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if bit != port:
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self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
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else:
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self.rbl_wordline_names[port].append("rbl_wl0_{0}_{1}".format(port, bit))
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self.rbl_wordline_names[port].append("rbl_wl1_{0}_{1}".format(port, bit))
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if bit != port:
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self.gnd_wordline_names.append("rbl0_wl_{0}_{1}".format(port, bit))
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self.gnd_wordline_names.append("rbl1_wl_{0}_{1}".format(port, bit))
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#else:
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# self.rbl_wordline_names[port].append("rbl_wl0_{0}_{1}".format(port, bit))
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# self.rbl_wordline_names[port].append("rbl_wl1_{0}_{1}".format(port, bit))
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# if bit != port:
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# self.gnd_wordline_names.append("rbl0_wl_{0}_{1}".format(port, bit))
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# self.gnd_wordline_names.append("rbl1_wl_{0}_{1}".format(port, bit))
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self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
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self.wordline_names = self.bitcell_array.wordline_names
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self.all_wordline_names = self.bitcell_array.all_wordline_names
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap.get_wordline_names()))
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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else:
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# All wordlines including dummy and RBL
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self.replica_array_wordline_names = []
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self.replica_array_wordline_names.extend(["gnd"] * 2)
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for bit in range(self.rbl[0]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
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self.replica_array_wordline_names.extend(self.all_wordline_names)
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for bit in range(self.rbl[1]):
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self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
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self.replica_array_wordline_names.extend(["gnd"] *2)
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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for port in range(self.rbl[0]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
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self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.supplies = ["vdd", "gnd"]
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else:
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self.supplies = ["vpwr", "vgnd"]
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# Used for names/dimensions only
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.cell = factory.create(module_type="bitcell")
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else:
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self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
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# Top/bottom dummy rows or col caps
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if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.supplies = ["vdd", "gnd"]
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# Used for names/dimensions only
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self.cell = factory.create(module_type="bitcell")
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
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# Replica columns
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self.replica_col_insts = []
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for port in self.all_ports:
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if port in self.rbls:
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self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port]))
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self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
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else:
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self.replica_col_insts.append(None)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_insts = []
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# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
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for port in self.all_ports:
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self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row))
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self.connect_inst([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
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# Top/bottom dummy rows or col caps
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap))
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@ -374,22 +352,9 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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mod=self.row_cap_right))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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else:
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self.dummy_row_insts = []
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
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mod=self.col_cap_bottom))
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self.connect_inst(self.all_bitline_names + self.supplies)
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self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
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mod=self.col_cap_top))
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self.connect_inst(self.all_bitline_names + self.supplies)
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from tech import custom_replica_bitcell_array_arrangement
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custom_replica_bitcell_array_arrangement(self)
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# Left/right Dummy columns
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self.dummy_col_insts = []
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
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mod=self.row_cap_left))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
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mod=self.row_cap_right))
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self.connect_inst(self.replica_array_wordline_names + self.supplies)
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def create_layout(self):
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# We will need unused wordlines grounded, so we need to know their layer
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@ -62,7 +62,11 @@ class replica_column(bitcell_base_array):
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def add_pins(self):
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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#remove 2 wordlines to account for top/bot
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if not cell_properties.bitcell.end_caps:
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self.create_all_wordline_names()
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else:
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self.create_all_wordline_names(2)
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self.add_pin_list(self.all_bitline_names, "OUTPUT")
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self.add_pin_list(self.all_wordline_names, "INPUT")
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Binary file not shown.
File diff suppressed because it is too large
Load Diff
BIN
missing_pin.gds
BIN
missing_pin.gds
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@ -6,13 +6,15 @@
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[globals/import_tech]: Importing technology: sky130
|
||||
[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
|
||||
[globals/init_paths]: Creating temp directory: /home/jesse/output/
|
||||
[verify/<module>]: Initializing verify...
|
||||
[verify/<module>]: LVS/DRC/PEX disabled.
|
||||
[characterizer/<module>]: Initializing characterizer...
|
||||
[characterizer/<module>]: Finding spice simulator.
|
||||
[verify/<module>]: Initializing verify...
|
||||
[verify/<module>]: LVS/DRC/PEX disabled.
|
||||
WARNING: file __init__.py: line 79: Did not find Magic.
|
||||
|
||||
[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
|
||||
|==============================================================================|
|
||||
|========= OpenRAM v1.1.5 =========|
|
||||
|========= OpenRAM v1.1.6 =========|
|
||||
|========= =========|
|
||||
|========= VLSI Design and Automation Lab =========|
|
||||
|========= Computer Science and Engineering Department =========|
|
||||
|
|
@ -23,7 +25,7 @@
|
|||
|========= Temp dir: /home/jesse/output/ =========|
|
||||
|========= See LICENSE for license info =========|
|
||||
|==============================================================================|
|
||||
** Start: 07/01/2020 04:43:37
|
||||
** Start: 10/07/2020 13:40:02
|
||||
Technology: sky130
|
||||
Total size: 256 bits
|
||||
Word size: 16
|
||||
|
|
@ -42,6 +44,7 @@ Performing simulation-based characterization with ngspice
|
|||
[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
|
||||
Words per row: 1
|
||||
Output files are:
|
||||
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.lvs
|
||||
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.sp
|
||||
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.v
|
||||
/home/jesse/openram/sram_0.05/sram_16_16_sky130_0.05.lib
|
||||
|
|
@ -55,198 +58,11 @@ Output files are:
|
|||
[dff_array/__init__]: Creating data_dff rows=1 cols=16
|
||||
[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
|
||||
[bank/__init__]: create sram of size 16 with 16 words
|
||||
[port_data/__init__]: create data port of size 16 with 1 words per row
|
||||
[precharge/__init__]: creating precharge cell precharge
|
||||
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
|
||||
[pgate/bin_width]: binning pmos tx, target: 0.55, found 0.55 x 1 = 0.55
|
||||
[precharge_array/__init__]: Creating precharge_array
|
||||
[precharge/__init__]: creating precharge cell precharge_0
|
||||
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
|
||||
[sense_amp_array/__init__]: Creating sense_amp_array
|
||||
[sense_amp/__init__]: Create sense_amp
|
||||
[write_driver_array/__init__]: Creating write_driver_array
|
||||
[write_driver/__init__]: Create write_driver
|
||||
[write_mask_and_array/__init__]: Creating write_mask_and_array
|
||||
[pand2/__init__]: Creating pand2 pand2
|
||||
[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12
|
||||
[pdriver/__init__]: creating pdriver pdriver
|
||||
[pinv/__init__]: creating pinv structure pinv with size of 2.0
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
|
||||
[pgate/bin_width]: binning pmos tx, target: 0.36, found 0.42 x 1 = 0.42
|
||||
[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
|
||||
[pinv/determine_tx_mults]: pinv bin count: 2 pinv bin error: 0.06481481481481488 percent error 0.03240740740740744
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12
|
||||
[port_data/__init__]: create data port of size 16 with 1 words per row
|
||||
[precharge_array/__init__]: Creating precharge_array_0
|
||||
[precharge/__init__]: creating precharge cell precharge_1
|
||||
[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
|
||||
[port_address/__init__]: create data port of cols 16 rows 16
|
||||
[and2_dec/__init__]: Creating and2_dec and2_dec
|
||||
[pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1
|
||||
[pinv/__init__]: creating pinv structure pinv_dec with size of 1
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.12 x 1 = 1.12
|
||||
[pgate/best_bin]: binning nmos tx, target: 0.36, found 1 x 0.36 = 0.36
|
||||
[pgate/best_bin]: binning pmos tx, target: 1.12, found 1 x 1.12 = 1.12
|
||||
[and3_dec/__init__]: Creating and3_dec and3_dec
|
||||
[wordline_driver_array/__init__]: Creating wordline_driver_array
|
||||
[wordline_driver/__init__]: Creating wordline_driver wordline_driver
|
||||
[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 16
|
||||
[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 16
|
||||
[pgate/bin_width]: binning nmos tx, target: 5.76, found 7.0 x 1 = 7.0
|
||||
[pgate/bin_width]: binning pmos tx, target: 17.28, found 7.0 x 3 = 21.0
|
||||
[pgate/bin_width]: binning nmos tx, target: 7.0, found 7.0 x 1 = 7.0
|
||||
[pgate/bin_width]: binning pmos tx, target: 7.0, found 7.0 x 1 = 7.0
|
||||
[replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 16
|
||||
[bitcell_base_array/__init__]: Creating bitcell_array 16 x 16
|
||||
[replica_bitcell_1rw_1r/__init__]: Create replica bitcell 1rw+1r object
|
||||
[dummy_bitcell_1rw_1r/__init__]: Create dummy bitcell 1rw+1r object
|
||||
[col_cap_bitcell_1rw_1r/__init__]: Create col_cap bitcell 1rw+1r object
|
||||
[bitcell_base_array/__init__]: Creating dummy_array 1 x 16
|
||||
[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16
|
||||
[bitcell_base_array/__init__]: Creating row_cap_array 20 x 1
|
||||
[row_cap_bitcell_1rw_1r/__init__]: Create row_cap bitcell 1rw+1r object
|
||||
[bitcell_base_array/__init__]: Creating row_cap_array_0 20 x 1
|
||||
[control_logic/__init__]: Creating control_logic_rw
|
||||
[dff_buf/__init__]: Creating dff_buf
|
||||
[pinv/__init__]: creating pinv structure pinv_0 with size of 2
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
|
||||
[pinv/determine_tx_mults]: pinv bin count: 4 pinv bin error: 0.12962962962962976 percent error 0.03240740740740744
|
||||
[pinv/__init__]: creating pinv structure pinv_1 with size of 4
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
|
||||
[pinv/determine_tx_mults]: pinv bin count: 6 pinv bin error: 0.44212962962962954 percent error 0.07368827160493825
|
||||
[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.6499999999999997, found 1.65 x 1 = 1.65
|
||||
[dff_buf_array/__init__]: Creating dff_buf_array
|
||||
[dff_buf/__init__]: Creating dff_buf_0
|
||||
[pand2/__init__]: Creating pand2 pand2_0
|
||||
[pnand2/__init__]: creating pnand2 structure pnand2_0 with size of 1
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[pdriver/__init__]: creating pdriver pdriver_0
|
||||
[pinv/__init__]: creating pinv structure pinv_2 with size of 12
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
|
||||
[pinv/determine_tx_mults]: pinv bin count: 8 pinv bin error: 0.6890432098765432 percent error 0.0861304012345679
|
||||
[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68
|
||||
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pbuf/__init__]: creating pbuf with size of 16
|
||||
[pinv/__init__]: creating pinv structure pinv_3 with size of 16
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
|
||||
[pinv/determine_tx_mults]: pinv bin count: 10 pinv bin error: 0.7723765432098766 percent error 0.07723765432098766
|
||||
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pdriver/__init__]: creating pdriver pdriver_1
|
||||
[pinv/__init__]: creating pinv structure pinv_4 with size of 1
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
|
||||
[pinv/determine_tx_mults]: pinv bin count: 12 pinv bin error: 0.8094135802469137 percent error 0.0674511316872428
|
||||
[pinv/__init__]: creating pinv structure pinv_5 with size of 1
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
|
||||
[pinv/determine_tx_mults]: pinv bin count: 14 pinv bin error: 0.8464506172839508 percent error 0.06046075837742505
|
||||
[pinv/__init__]: creating pinv structure pinv_6 with size of 4
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
|
||||
[pinv/determine_tx_mults]: pinv bin count: 16 pinv bin error: 1.1589506172839505 percent error 0.07243441358024691
|
||||
[pinv/__init__]: creating pinv structure pinv_7 with size of 13
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 14.04, found 2.0 x 8 = 16.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.68, found 1.68 x 3 = 5.04
|
||||
[pinv/determine_tx_mults]: pinv bin count: 18 pinv bin error: 1.3754748338081673 percent error 0.07641526854489818
|
||||
[pgate/bin_width]: binning nmos tx, target: 1.68, found 1.68 x 1 = 1.68
|
||||
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pinv/__init__]: creating pinv structure pinv_8 with size of 38
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 41.04, found 2.0 x 21 = 42.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.68, found 2.0 x 7 = 14.0
|
||||
[pinv/determine_tx_mults]: pinv bin count: 20 pinv bin error: 1.4222584595391614 percent error 0.07111292297695807
|
||||
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pdriver/__init__]: creating pdriver pdriver_2
|
||||
[pinv/__init__]: creating pinv structure pinv_9 with size of 2
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
|
||||
[pinv/determine_tx_mults]: pinv bin count: 22 pinv bin error: 1.4870732743539763 percent error 0.06759423974336255
|
||||
[pinv/__init__]: creating pinv structure pinv_10 with size of 5
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 5.3999999999999995, found 2.0 x 3 = 6.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.7999999999999998, found 2.0 x 1 = 2.0
|
||||
[pinv/determine_tx_mults]: pinv bin count: 24 pinv bin error: 1.7092954965761986 percent error 0.07122064569067495
|
||||
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pand3/__init__]: Creating pand3 pand3
|
||||
[pnand3/__init__]: creating pnand3 structure pnand3 with size of 1
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.74 x 1 = 0.74
|
||||
[pdriver/__init__]: creating pdriver pdriver_3
|
||||
[pinv/__init__]: creating pinv structure pinv_11 with size of 24
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 25.919999999999998, found 2.0 x 13 = 26.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 8.64, found 2.0 x 5 = 10.0
|
||||
[pinv/determine_tx_mults]: pinv bin count: 26 pinv bin error: 1.8697893237366925 percent error 0.07191497398987279
|
||||
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pand3/__init__]: Creating pand3 pand3_0
|
||||
[pdriver/__init__]: creating pdriver pdriver_4
|
||||
[pinv/__init__]: creating pinv structure pinv_12 with size of 16
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
|
||||
[pinv/determine_tx_mults]: pinv bin count: 28 pinv bin error: 1.9531226570700257 percent error 0.06975438060964377
|
||||
[pinv/__init__]: creating pinv structure pinv_13 with size of 1
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
|
||||
[pinv/determine_tx_mults]: pinv bin count: 30 pinv bin error: 1.9901596941070627 percent error 0.06633865647023543
|
||||
[pnand2/__init__]: creating pnand2 structure pnand2_1 with size of 1
|
||||
[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
|
||||
[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
|
||||
[pinv/__init__]: creating pinv structure pinv_14 with size of 1
|
||||
[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
|
||||
[pinv/determine_tx_mults]: pinv bin count: 32 pinv bin error: 2.0271967311441 percent error 0.06334989784825312
|
||||
[control_logic/__init__]: Creating control_logic_r
|
||||
[dff_buf_array/__init__]: Creating dff_buf_array_0
|
||||
[pdriver/__init__]: creating pdriver pdriver_5
|
||||
[pinv/__init__]: creating pinv structure pinv_15 with size of 12
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
|
||||
[pinv/determine_tx_mults]: pinv bin count: 34 pinv bin error: 2.2741103113910133 percent error 0.06688559739385333
|
||||
[pinv/__init__]: creating pinv structure pinv_16 with size of 37
|
||||
[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
|
||||
[pinv/determine_tx_mults]: prebinning pmos tx, target: 39.96, found 2.0 x 20 = 40.0
|
||||
[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.32, found 2.0 x 7 = 14.0
|
||||
[pinv/determine_tx_mults]: pinv bin count: 36 pinv bin error: 2.3261623634430655 percent error 0.06461562120675182
|
||||
[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
|
||||
** Submodules: 8.6 seconds
|
||||
** Placement: 0.0 seconds
|
||||
*** Init supply router: 56.2 seconds
|
||||
[supply_hannan_router/route]: Running hannan supply router on vdd and gnd...
|
||||
[supply_hannan_router/retrieve_pins]: Retrieving pins for vdd.
|
||||
[supply_hannan_router/retrieve_pins]: Retrieving pins for gnd.
|
||||
[supply_hannan_router/route]: Building matrix
|
||||
[and4_dec/__init__]: Creating and4_dec and4_dec
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
[globals/get_tool]: Using PEX: /usr/local/bin/magic
|
||||
[globals/get_tool]: Using GDS: /usr/local/bin/magic
|
||||
[bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4
|
||||
[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4
|
||||
[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4 rbls: [1, 0] left_rbl: None right_rbl: None
|
||||
[bitcell_base_array/__init__]: Creating bitcell_array 4 x 4
|
||||
[bitcell_base_array/__init__]: Creating dummy_array 1 x 4
|
||||
[bitcell_array/__init__]: Creating bitcell_array 4 x 4
|
||||
[bitcell_base_array/__init__]: Creating replica_column 7 x 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue