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fixed port_data typo

This commit is contained in:
Jesse Cirimelli-Low 2021-05-03 14:39:51 -07:00
parent 31364e508e
commit 4377619bf6
1 changed files with 2 additions and 0 deletions
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2
compiler/modules/port_data.py
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@ -44,6 +44,8 @@ class port_data(design.design):
if(cell_properties.use_strap == True and OPTS.num_ports == 1):
strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version)
precharge_width = bitcell.width + strap.width
else:
precharge_width = bitcell.width
self.bit_offsets = []
for i in range(self.num_cols + self.num_spare_cols):
self.bit_offsets.append(i * precharge_width)