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Move rbl route away from bitcell array

This commit is contained in:
mrg 2020-03-06 09:48:20 -08:00
parent ee18f61cbf
commit 1a2efd77ad
1 changed files with 2 additions and 2 deletions
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4
compiler/modules/bank.py
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@ -128,10 +128,10 @@ class bank(design.design):
bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name)
# This will ensure the pin is only on the top or bottom edge
if port % 2:
via_offset = bl_pin.uc()
via_offset = bl_pin.uc() + vector(0, self.m2_pitch)
left_right_offset = vector(self.max_x_offset, via_offset.y)
else:
via_offset = bl_pin.bc()
via_offset = bl_pin.bc() - vector(0, self.m2_pitch)
left_right_offset = vector(self.min_x_offset, via_offset.y)
if bl_pin == "m1":
self.add_via_center(layers=self.m1_stack,