mirror of https://github.com/VLSIDA/OpenRAM.git
Move pnand outputs to M1. Debug hierarchical decoder multirow.
This commit is contained in:
mrg
parent
2e67d44cd7
commit
43dcf675a1
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@ -199,7 +199,8 @@ class hierarchical_decoder(design.design):
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self.input_routing_width = (self.num_inputs + 1) * self.m2_pitch
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# Calculates height and width of hierarchical decoder
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self.height = max(self.predecoder_height, self.row_decoder_height)
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# Add extra pitch for good measure
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self.height = max(self.predecoder_height, self.row_decoder_height) + self.m3_pitch
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self.width = self.input_routing_width + self.predecoder_width \
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+ self.internal_routing_width \
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+ self.decoders_per_row * nand_width + self.inv.width
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@ -261,7 +262,10 @@ class hierarchical_decoder(design.design):
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self.route_input_bus(decoder_offset, input_offset)
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def route_input_bus(self, input_offset, output_offset):
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""" Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """
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"""
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Route a vertical M2 coordinate to another
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vertical M2 coordinate to the predecode inputs
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"""
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self.add_via_center(layers=self.m2_stack,
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offset=input_offset)
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@ -471,10 +475,10 @@ class hierarchical_decoder(design.design):
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names=input_bus_names,
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length=self.height)
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self.route_bus_to_predecodes()
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self.route_predecodes_to_bus()
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self.route_bus_to_decoder()
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def route_bus_to_predecodes(self):
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def route_predecodes_to_bus(self):
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"""
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Iterates through all of the predecodes
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and connects to the rails including the offsets
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@ -517,7 +521,7 @@ class hierarchical_decoder(design.design):
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if (output_index < self.num_outputs):
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row_index = math.floor(output_index / self.decoders_per_row)
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row_remainder = (output_index % self.decoders_per_row)
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row_offset = row_index * self.and_inst[0].height + (2 * row_remainder + 4) * self.m1_pitch
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row_offset = row_index * self.and_inst[0].height + (2 * row_remainder + 1) * self.m3_pitch
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_bus_outputs(predecode_name,
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self.and_inst[output_index].get_pin("A"),
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@ -525,7 +529,7 @@ class hierarchical_decoder(design.design):
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_bus_outputs(predecode_name,
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self.and_inst[output_index].get_pin("B"),
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row_offset + self.m1_pitch)
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row_offset + self.m3_pitch)
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output_index = output_index + 1
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elif (self.num_inputs > 5):
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@ -536,7 +540,7 @@ class hierarchical_decoder(design.design):
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if (output_index < self.num_outputs):
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row_index = math.floor(output_index / self.decoders_per_row)
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row_remainder = (output_index % self.decoders_per_row)
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row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 4) * self.m1_pitch
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row_offset = row_index * self.and_inst[0].height + (3 * row_remainder + 1) * self.m3_pitch
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_bus_outputs(predecode_name,
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self.and_inst[output_index].get_pin("A"),
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@ -544,11 +548,11 @@ class hierarchical_decoder(design.design):
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_bus_outputs(predecode_name,
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self.and_inst[output_index].get_pin("B"),
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row_offset + self.m1_pitch)
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row_offset + self.m3_pitch)
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predecode_name = "predecode_{}".format(index_C)
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self.route_predecode_bus_outputs(predecode_name,
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self.and_inst[output_index].get_pin("C"),
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row_offset + 2 * self.m1_pitch)
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row_offset + 2 * self.m3_pitch)
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output_index = output_index + 1
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def route_vdd_gnd(self):
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@ -557,13 +561,19 @@ class hierarchical_decoder(design.design):
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must-connects next level up.
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"""
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# The vias will be placed in the center and right of the cells, respectively.
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xoffset = self.and_inst[0].rx()
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# The vias will be placed at the right of the cells.
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xoffset = max(x.rx() for x in self.and_inst)
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for num in range(0, self.num_outputs):
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# Only add the power pin for the 1st in each row
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if num % self.decoders_per_row:
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continue
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for pin_name in ["vdd", "gnd"]:
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# The nand and inv are the same height rows...
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supply_pin = self.and_inst[num].get_pin(pin_name)
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pin_pos = vector(xoffset, supply_pin.cy())
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self.add_path("m1",
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[supply_pin.lc(), vector(xoffset, supply_pin.cy())])
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self.add_power_pin(name=pin_name,
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loc=pin_pos)
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@ -98,7 +98,7 @@ class pnand2(pgate.pgate):
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# metal spacing to allow contacts on any layer
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self.input_spacing = max(self.poly_space + contact.poly_contact.first_layer_width,
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self.m1_space + contact.m1_via.first_layer_width,
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self.m2_space + contact.m2_via.first_layer_width,
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self.m2_space + contact.m2_via.first_layer_width,
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self.m3_space + contact.m2_via.second_layer_width)
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@ -173,13 +173,15 @@ class pnand2(pgate.pgate):
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0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos_nd.active_height))
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def add_well_contacts(self):
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"""
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"""
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Add n/p well taps to the layout and connect to supplies
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AFTER the wells are created
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"""
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self.add_nwell_contact(self.pmos, self.pmos2_pos)
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self.add_pwell_contact(self.nmos_nd, self.nmos2_pos)
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self.add_nwell_contact(self.pmos,
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self.pmos2_pos + vector(self.m1_pitch, 0))
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self.add_pwell_contact(self.nmos_nd,
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self.nmos2_pos + vector(self.m1_pitch, 0))
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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@ -197,7 +199,7 @@ class pnand2(pgate.pgate):
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self.nmos2_inst,
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inputB_yoffset,
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"B",
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position="right")
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position="center")
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# This will help with the wells and the input/output placement
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self.inputA_yoffset = self.pmos2_inst.by() - self.poly_extend_active \
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@ -209,6 +211,7 @@ class pnand2(pgate.pgate):
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def route_output(self):
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""" Route the Z output """
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# PMOS1 drain
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pmos_pin = self.pmos1_inst.get_pin("D")
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top_pin_offset = pmos_pin.center()
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@ -217,29 +220,46 @@ class pnand2(pgate.pgate):
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bottom_pin_offset = nmos_pin.center()
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# Output pin
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out_offset = vector(nmos_pin.center().x + self.m1_pitch,
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c_pin = self.get_pin("B")
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out_offset = vector(c_pin.cx() + self.m1_pitch,
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self.inputA_yoffset)
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# Midpoints of the L routes go horizontal first then vertical
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mid1_offset = vector(out_offset.x, top_pin_offset.y)
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# This routes on M2
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# # Midpoints of the L routes go horizontal first then vertical
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# mid1_offset = vector(out_offset.x, top_pin_offset.y)
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# mid2_offset = vector(out_offset.x, bottom_pin_offset.y)
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# # Non-preferred active contacts
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# self.add_via_center(layers=self.m1_stack,
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# directions=("V", "H"),
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# offset=pmos_pin.center())
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# # Non-preferred active contacts
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# self.add_via_center(layers=self.m1_stack,
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# directions=("V", "H"),
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# offset=nmos_pin.center())
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# self.add_via_center(layers=self.m1_stack,
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# offset=out_offset)
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# # PMOS1 to mid-drain to NMOS2 drain
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# self.add_path("m2",
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# [top_pin_offset, mid1_offset, out_offset,
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# mid2_offset, bottom_pin_offset])
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# This routes on M1
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# Midpoints of the L routes goes vertical first then horizontal
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mid1_offset = vector(top_pin_offset.x, out_offset.y)
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# Midpoints of the L routes goes horizontal first then vertical
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mid2_offset = vector(out_offset.x, bottom_pin_offset.y)
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# Non-preferred active contacts
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self.add_via_center(layers=self.m1_stack,
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directions=("V", "H"),
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offset=pmos_pin.center())
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# Non-preferred active contacts
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self.add_via_center(layers=self.m1_stack,
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directions=("V", "H"),
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offset=nmos_pin.center())
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self.add_via_center(layers=self.m1_stack,
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offset=out_offset)
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self.add_path("m1",
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[top_pin_offset, mid1_offset, out_offset])
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# Route in two segments to have the width rule
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self.add_path("m1",
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[bottom_pin_offset, mid2_offset + vector(0.5 * self.m1_width, 0)],
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width=nmos_pin.height())
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self.add_path("m1",
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[mid2_offset, out_offset])
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# PMOS1 to mid-drain to NMOS2 drain
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self.add_path("m2",
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[top_pin_offset, mid1_offset, out_offset,
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mid2_offset, bottom_pin_offset])
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# This extends the output to the edge of the cell
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self.add_layout_pin_rect_center(text="Z",
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layer="m1",
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@ -191,8 +191,10 @@ class pnand3(pgate.pgate):
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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self.add_nwell_contact(self.pmos, self.pmos3_pos)
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self.add_pwell_contact(self.nmos_ns, self.nmos3_pos)
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self.add_nwell_contact(self.pmos,
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self.pmos3_pos + vector(self.m1_pitch, 0))
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self.add_pwell_contact(self.nmos_ns,
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self.nmos3_pos + vector(self.m1_pitch, 0))
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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@ -221,7 +223,7 @@ class pnand3(pgate.pgate):
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self.nmos3_inst,
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self.inputC_yoffset,
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"C",
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position="left")
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position="right")
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# FIXME: constant hack
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if OPTS.tech_name == "s8":
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@ -236,6 +238,7 @@ class pnand3(pgate.pgate):
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def route_output(self):
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""" Route the Z output """
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# PMOS1 drain
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pmos1_pin = self.pmos1_inst.get_pin("D")
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# PMOS3 drain
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@ -243,29 +246,56 @@ class pnand3(pgate.pgate):
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# NMOS3 drain
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nmos3_pin = self.nmos3_inst.get_pin("D")
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# Go up to metal2 for ease on all output pins
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self.add_via_center(layers=self.m1_stack,
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offset=pmos1_pin.center(),
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directions=("V", "V"))
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self.add_via_center(layers=self.m1_stack,
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offset=pmos3_pin.center(),
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directions=("V", "V"))
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self.add_via_center(layers=self.m1_stack,
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offset=nmos3_pin.center(),
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directions=("V", "V"))
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# midpoint for routing
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mid_offset = vector(nmos3_pin.cx() + self.m1_pitch,
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self.inputA_yoffset)
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# Aligned with the well taps
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out_offset = vector(self.nwell_contact.cx(),
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self.inputA_yoffset)
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# PMOS3 and NMOS3 are drain aligned
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self.add_path("m1", [pmos3_pin.center(), nmos3_pin.center()])
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# Route in the A input track (top track)
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mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset)
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self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()])
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# Go up to metal2 for ease on all output pins
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# self.add_via_center(layers=self.m1_stack,
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# offset=pmos1_pin.center(),
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# directions=("V", "V"))
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# self.add_via_center(layers=self.m1_stack,
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# offset=pmos3_pin.center(),
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# directions=("V", "V"))
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# self.add_via_center(layers=self.m1_stack,
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# offset=nmos3_pin.center(),
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# directions=("V", "V"))
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# # Route in the A input track (top track)
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# mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset)
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# self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()])
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# This extends the output to the edge of the cell
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self.add_via_center(layers=self.m1_stack,
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offset=mid_offset)
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# self.add_via_center(layers=self.m1_stack,
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# offset=mid_offset)
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top_left_pin_offset = pmos1_pin.center()
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top_right_pin_offset = pmos3_pin.center()
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bottom_pin_offset = nmos3_pin.center()
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# PMOS1 to output
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self.add_path("m1", [top_left_pin_offset,
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vector(top_left_pin_offset.x, out_offset.y),
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out_offset])
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# PMOS3 to output
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self.add_path("m1", [top_right_pin_offset,
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vector(top_right_pin_offset.x, mid_offset.y),
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mid_offset])
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# NMOS3 to output
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mid2_offset = vector(mid_offset.x, bottom_pin_offset.y)
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self.add_path("m1",
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[bottom_pin_offset, mid2_offset],
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width=nmos3_pin.height())
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mid3_offset = vector(mid_offset.x, nmos3_pin.by())
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self.add_path("m1", [mid3_offset, mid_offset])
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self.add_layout_pin_rect_center(text="Z",
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layer="m1",
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offset=mid_offset,
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offset=out_offset,
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width=contact.m1_via.first_layer_width,
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height=contact.m1_via.first_layer_height)
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@ -471,13 +471,13 @@ class ptx(design.design):
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"""Returns an object representing the parameters for delay in tau units."""
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# FIXME: Using the same definition as the pinv.py.
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parasitic_delay = 1
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size = self.mults*self.tx_width/drc("minwidth_tx")
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return logical_effort.logical_effort(self.name,
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size,
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self.input_load(),
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cout,
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parasitic_delay)
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parasitic_delay = 1
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size = self.mults * self.tx_width / drc("minwidth_tx")
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return logical_effort.logical_effort(self.name,
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size,
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self.input_load(),
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cout,
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parasitic_delay)
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def input_load(self):
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"""
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@ -485,7 +485,7 @@ class ptx(design.design):
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"""
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# FIXME: this will be applied for the loads of the drain/source
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return self.mults*self.tx_width/drc("minwidth_tx")
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return self.mults * self.tx_width / drc("minwidth_tx")
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def add_diff_contact(self, label, pos):
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contact=self.add_via_center(layers=self.active_stack,
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@ -496,14 +496,25 @@ class ptx(design.design):
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well_type=self.well_type)
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if hasattr(self, "li_stack"):
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self.add_via_center(layers=self.li_stack,
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offset=pos)
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contact=self.add_via_center(layers=self.li_stack,
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offset=pos,
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directions=("V", "V"))
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# contact_area = contact.mod.second_layer_width * contact.mod.second_layer_height
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# min_area = drc("minarea_m1")
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# width = contact.mod.second_layer_width
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# if contact_area < min_area:
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# height = min_area / width
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# else:
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# height = contact.mod.second_layer_height
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width = contact.mod.second_layer_width
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height = contact.mod.second_layer_height
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self.add_layout_pin_rect_center(text=label,
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layer="m1",
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offset=pos,
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width=contact.mod.second_layer_width,
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height=contact.mod.second_layer_height)
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width=width,
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height=height)
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return(contact)
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def get_cin(self):
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