mirror of https://github.com/VLSIDA/OpenRAM.git
Change default options for replica_bitcell_array
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@ -390,10 +390,7 @@ class bank(design.design):
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else:
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self.bitcell_array = factory.create(module_type="replica_bitcell_array",
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cols=self.num_cols + self.num_spare_cols,
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rows=self.num_rows,
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rbl=[1, 1 if len(self.all_ports)>1 else 0],
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left_rbl=[0],
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right_rbl=[1] if len(self.all_ports) > 1 else [])
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rows=self.num_rows)
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self.add_mod(self.bitcell_array)
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if(self.num_banks > 1):
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@ -21,7 +21,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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Requires a regular bitcell array, replica bitcell, and dummy
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bitcell (Bl/BR disconnected).
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"""
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def __init__(self, rows, cols, rbl, name, left_rbl=[], right_rbl=[]):
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def __init__(self, rows, cols, name, rbl=None, left_rbl=[0], right_rbl=[]):
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super().__init__(name, rows, cols, column_offset=0)
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debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
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rows,
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@ -35,20 +35,26 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.column_size = cols
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self.row_size = rows
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# This is how many RBLs are in all the arrays
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self.rbl = rbl
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if rbl:
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self.rbl = rbl
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else:
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self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
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# This specifies which RBL to put on the left or right
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# by port number
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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if right_rbl:
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self.right_rbl = right_rbl
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else:
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self.right_rbl=[1] if len(self.all_ports) > 1 else []
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self.rbls = self.left_rbl + self.right_rbl
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debug.check(sum(rbl) == len(self.all_ports),
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debug.check(sum(self.rbl) == len(self.all_ports),
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"Invalid number of RBLs for port configuration.")
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debug.check(sum(rbl) >= len(self.left_rbl) + len(self.right_rbl),
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debug.check(sum(self.rbl) >= len(self.left_rbl) + len(self.right_rbl),
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"Invalid number of RBLs for port configuration.")
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# Two dummy rows plus replica even if we don't add the column
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self.extra_rows = 2 + sum(rbl)
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self.extra_rows = 2 + sum(self.rbl)
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# Two dummy cols plus replica if we add the column
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self.extra_cols = 2 + len(self.left_rbl) + len(self.right_rbl)
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