mirror of https://github.com/VLSIDA/OpenRAM.git
Update replica column unit tests for new refactor
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@ -15,18 +15,17 @@ class replica_column(design.design):
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"""
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Generate a replica bitline column for the replica array.
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Rows is the total number of rows i the main array.
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Left_rbl and right_rbl are the number of left and right replica bitlines.
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rbl is a tuple with the number of left and right replica bitlines.
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Replica bit specifies which replica column this is (to determine where to put the
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replica cell.
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replica cell relative to the bottom (including the dummy bit at 0).
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"""
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def __init__(self, name, rows, left_rbl, right_rbl, replica_bit,
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column_offset=0):
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def __init__(self, name, rows, rbl, replica_bit, column_offset=0):
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super().__init__(name)
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self.rows = rows
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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self.replica_bit = replica_bit
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# left, right, regular rows plus top/bottom dummy cells
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self.total_size = self.left_rbl + rows + self.right_rbl + 2
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@ -34,10 +33,10 @@ class replica_column(design.design):
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debug.check(replica_bit != 0 and replica_bit != rows,
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"Replica bit cannot be the dummy row.")
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debug.check(replica_bit <= left_rbl or replica_bit >= self.total_size - right_rbl - 1,
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debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1,
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"Replica bit cannot be in the regular array.")
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if OPTS.tech_name == "sky130":
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debug.check(rows % 2 == 0 and (left_rbl + 1) % 2 == 0,
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debug.check(rows % 2 == 0 and (self.left_rbl + 1) % 2 == 0,
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"sky130 currently requires rows to be even and to start with X mirroring"
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+ " (left_rbl must be odd) for LVS.")
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