mirror of https://github.com/VLSIDA/OpenRAM.git
update to sense amp and write driver modules
This commit is contained in:
Joey Kunzler
parent
9907daaffa
commit
b0d2946c80
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@ -22,7 +22,7 @@ class sense_amp_array(design.design):
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def __init__(self, name, word_size, words_per_row):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("words_per_row: {0}".format(words_per_row))
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self.word_size = word_size
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@ -56,7 +56,7 @@ class sense_amp_array(design.design):
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def create_layout(self):
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self.height = self.amp.height
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if self.bitcell.width > self.amp.width:
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self.width = self.bitcell.width * self.word_size * self.words_per_row
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else:
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@ -76,16 +76,16 @@ class sense_amp_array(design.design):
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self.add_pin(self.en_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.amp = factory.create(module_type="sense_amp")
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self.add_mod(self.amp)
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# This is just used for measurements,
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# so don't add the module
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self.bitcell = factory.create(module_type="bitcell")
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def create_sense_amp_array(self):
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self.local_insts = []
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for i in range(0,self.word_size):
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@ -121,11 +121,11 @@ class sense_amp_array(design.design):
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amp_position = vector(xoffset, 0)
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self.local_insts[i].place(offset=amp_position,mirror=mirror)
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def add_layout_pins(self):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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self.add_power_pin(name = "gnd",
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loc = inst.get_pin("gnd").center(),
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start_layer="m2",
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@ -141,40 +141,41 @@ class sense_amp_array(design.design):
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dout_pin = inst.get_pin(inst.mod.dout_name)
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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layer="m2",
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=bl_pin.height())
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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layer="m2",
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layer=br_pin.layer,
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=br_pin.height())
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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layer="m2",
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layer=dout_pin.layer,
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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def route_rails(self):
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# add sclk rail across entire array
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sclk = self.amp.get_pin(self.amp.en_name)
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sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1)
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self.add_layout_pin(text=self.en_name,
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layer="m1",
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layer=sclk.layer,
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offset=sclk_offset,
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width=self.width,
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height=drc("minwidth_m1"))
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height=drc("minwidth_" + sclk.layer))
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def input_load(self):
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return self.amp.input_load()
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def get_en_cin(self):
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"""Get the relative capacitance of all the sense amp enable connections in the array"""
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sense_amp_en_cin = self.amp.get_en_cin()
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return sense_amp_en_cin * self.word_size
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the PMOS isolation TX"""
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from tech import parameter
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@ -23,7 +23,7 @@ class write_driver_array(design.design):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("word_size {0}".format(word_size))
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self.columns = columns
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self.word_size = word_size
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@ -57,15 +57,15 @@ class write_driver_array(design.design):
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self.add_modules()
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self.add_pins()
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self.create_write_array()
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def create_layout(self):
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if self.bitcell.width > self.driver.width:
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self.width = self.columns * self.bitcell.width
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else:
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self.width = self.columns * self.driver.width
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self.height = self.driver.height
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self.place_write_array()
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self.add_layout_pins()
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self.add_boundary()
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@ -139,26 +139,26 @@ class write_driver_array(design.design):
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base = vector(xoffset, 0)
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self.driver_insts[index].place(offset=base, mirror=mirror)
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def add_layout_pins(self):
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for i in range(self.word_size):
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inst = self.driver_insts[i]
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din_pin = inst.get_pin(inst.mod.din_name)
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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layer="m2",
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layer=din_pin.layer,
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offset=din_pin.ll(),
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width=din_pin.width(),
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height=din_pin.height())
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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layer="m2",
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=bl_pin.height())
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br_pin = inst.get_pin(inst.mod.get_br_names())
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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layer="m2",
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layer=br_pin.layer,
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=br_pin.height())
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@ -194,7 +194,7 @@ class write_driver_array(design.design):
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width=self.width)
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def get_w_en_cin(self):
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"""Get the relative capacitance of all the enable connections in the bank"""
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@ -22,6 +22,10 @@ class sense_amp_test(openram_test):
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globals.init_openram(config_file)
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# check sense amp array for single port
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debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
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a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
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self.local_check(a)
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debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
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a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
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self.local_check(a)
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@ -29,7 +33,7 @@ class sense_amp_test(openram_test):
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debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
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a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
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self.local_check(a)
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# check sense amp array for multi-port
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OPTS.bitcell = "pbitcell"
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OPTS.num_rw_ports = 1
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@ -44,9 +48,9 @@ class sense_amp_test(openram_test):
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debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
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a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
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self.local_check(a)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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