mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 Formatting
This commit is contained in:
mrg
parent
287a31f598
commit
7adeef6c9e
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@ -1,18 +1,17 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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import sys
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from tech import drc, parameter
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from tech import drc
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import debug
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import design
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from sram_factory import factory
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from collections import namedtuple
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from vector import vector
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from globals import OPTS
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class port_data(design.design):
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"""
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Create the data port (column mux, sense amps, write driver, etc.) for the given port number.
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@ -24,18 +23,21 @@ class port_data(design.design):
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sram_config.set_local_config(self)
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self.port = port
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if self.write_size is not None:
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self.num_wmasks = int(self.word_size/self.write_size)
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self.num_wmasks = int(self.word_size / self.write_size)
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else:
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self.num_wmasks = 0
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if name == "":
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name = "port_data_{0}".format(self.port)
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design.design.__init__(self, name)
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debug.info(2, "create data port of size {0} with {1} words per row".format(self.word_size,self.words_per_row))
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debug.info(2,
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"create data port of size {0} with {1} words per row".format(self.word_size,
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self.words_per_row))
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self.create_netlist()
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if not OPTS.netlist_only:
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debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.")
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debug.check(len(self.all_ports)<=2,
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"Bank layout cannot handle more than two ports.")
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self.create_layout()
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self.add_boundary()
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@ -93,8 +95,6 @@ class port_data(design.design):
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else:
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self.column_mux_array_inst = None
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def create_layout(self):
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self.compute_instance_offsets()
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self.place_instances()
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@ -104,33 +104,32 @@ class port_data(design.design):
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def add_pins(self):
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""" Adding pins for port address module"""
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self.add_pin("rbl_bl","INOUT")
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self.add_pin("rbl_br","INOUT")
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self.add_pin("rbl_bl", "INOUT")
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self.add_pin("rbl_br", "INOUT")
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for bit in range(self.num_cols):
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bl_name = self.get_bl_name(self.port)
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br_name = self.get_br_name(self.port)
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self.add_pin("{0}_{1}".format(bl_name, bit),"INOUT")
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self.add_pin("{0}_{1}".format(br_name, bit),"INOUT")
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self.add_pin("{0}_{1}".format(bl_name, bit), "INOUT")
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self.add_pin("{0}_{1}".format(br_name, bit), "INOUT")
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if self.port in self.read_ports:
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for bit in range(self.word_size):
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self.add_pin("dout_{}".format(bit),"OUTPUT")
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self.add_pin("dout_{}".format(bit), "OUTPUT")
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if self.port in self.write_ports:
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for bit in range(self.word_size):
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self.add_pin("din_{}".format(bit),"INPUT")
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self.add_pin("din_{}".format(bit), "INPUT")
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# Will be empty if no col addr lines
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sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)]
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for pin_name in sel_names:
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self.add_pin(pin_name,"INPUT")
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self.add_pin(pin_name, "INPUT")
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if self.port in self.read_ports:
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self.add_pin("s_en", "INPUT")
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self.add_pin("p_en_bar", "INPUT")
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if self.port in self.write_ports:
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self.add_pin("w_en", "INPUT")
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for bit in range(self.num_wmasks):
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self.add_pin("bank_wmask_{}".format(bit),"INPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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self.add_pin("bank_wmask_{}".format(bit), "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def route_layout(self):
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""" Create routing among the modules """
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@ -172,8 +171,8 @@ class port_data(design.design):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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for inst in self.insts:
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self.copy_power_pins(inst,"vdd")
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self.copy_power_pins(inst,"gnd")
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self.copy_power_pins(inst, "vdd")
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self.copy_power_pins(inst, "gnd")
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def add_modules(self):
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@ -193,7 +192,6 @@ class port_data(design.design):
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else:
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self.sense_amp_array = None
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if self.col_addr_size > 0:
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self.column_mux_array = factory.create(module_type="column_mux_array",
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columns=self.num_cols,
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@ -204,7 +202,6 @@ class port_data(design.design):
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else:
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self.column_mux_array = None
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if self.port in self.write_ports:
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self.write_driver_array = factory.create(module_type="write_driver_array",
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columns=self.num_cols,
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@ -234,29 +231,27 @@ class port_data(design.design):
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else:
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self.num_col_addr_lines = 0
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# A space for wells or jogging m2 between modules
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self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"),
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3*self.m2_pitch)
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self.m2_gap = max(2 * drc("pwell_to_nwell") + drc("nwell_enclose_active"),
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3 * self.m2_pitch)
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# create arrays of bitline and bitline_bar names for read, write, or all ports
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# create arrays of bitline and bitline_bar names for read,
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# write, or all ports
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self.bitcell = factory.create(module_type="bitcell")
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self.bl_names = self.bitcell.get_all_bl_names()
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self.br_names = self.bitcell.get_all_br_names()
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self.wl_names = self.bitcell.get_all_wl_names()
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# used for bl/br names
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self.precharge = factory.create(module_type="precharge",
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bitcell_bl = self.bl_names[0],
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bitcell_br = self.br_names[0])
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bitcell_bl=self.bl_names[0],
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bitcell_br=self.br_names[0])
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# We create a dummy here to get bl/br names to add those pins to this
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# module, which happens before we create the real precharge_array
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self.precharge_array = factory.create(module_type="precharge_array",
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columns=self.num_cols + 1,
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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columns=self.num_cols + 1,
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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def create_precharge_array(self):
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""" Creating Precharge """
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@ -285,13 +280,11 @@ class port_data(design.design):
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temp.extend(["p_en_bar", "vdd"])
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self.connect_inst(temp)
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def place_precharge_array(self, offset):
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""" Placing Precharge """
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self.precharge_array_inst.place(offset=offset, mirror="MX")
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def create_column_mux_array(self):
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""" Creating Column Mux when words_per_row > 1 . """
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temp.append("gnd")
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self.connect_inst(temp)
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def place_column_mux_array(self, offset):
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""" Placing Column Mux when words_per_row > 1 . """
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if self.col_addr_size == 0:
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@ -322,7 +314,6 @@ class port_data(design.design):
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self.column_mux_array_inst.place(offset=offset, mirror="MX")
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def create_sense_amp_array(self):
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""" Creating Sense amp """
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self.sense_amp_array_inst = self.add_inst(name="sense_amp_array{}".format(self.port),
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@ -340,16 +331,13 @@ class port_data(design.design):
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temp.append("{0}_out_{1}".format(bl_name, bit))
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temp.append("{0}_out_{1}".format(br_name, bit))
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temp.extend(["s_en", "vdd", "gnd"])
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self.connect_inst(temp)
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def place_sense_amp_array(self, offset):
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""" Placing Sense amp """
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self.sense_amp_array_inst.place(offset=offset, mirror="MX")
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def create_write_driver_array(self):
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""" Creating Write Driver """
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self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port),
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@ -378,12 +366,10 @@ class port_data(design.design):
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self.connect_inst(temp)
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def place_write_driver_array(self, offset):
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""" Placing Write Driver """
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self.write_driver_array_inst.place(offset=offset, mirror="MX")
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def create_write_mask_and_array(self):
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""" Creating Write Mask AND Array """
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self.write_mask_and_array_inst = self.add_inst(name="write_mask_and_array{}".format(self.port),
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@ -398,12 +384,10 @@ class port_data(design.design):
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def place_write_mask_and_array(self, offset):
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""" Placing Write Mask AND array """
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self.write_mask_and_array_inst.place(offset=offset, mirror="MX")
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def compute_instance_offsets(self):
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"""
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Compute the empty instance offsets for port0 and port1 (if needed)
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if self.column_mux_offset:
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self.place_column_mux_array(self.column_mux_offset)
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def route_sense_amp_out(self, port):
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""" Add pins for the sense amp output """
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for bit in range(self.word_size):
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data_pin = self.sense_amp_array_inst.get_pin("data_{}".format(bit))
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self.add_layout_pin_rect_center(text="dout_{0}".format(bit),
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layer=data_pin.layer,
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layer=data_pin.layer,
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width())
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def route_write_driver_in(self, port):
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""" Connecting write driver """
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@ -479,7 +461,6 @@ class port_data(design.design):
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din_name = "din_{}".format(row)
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self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name)
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def route_write_mask_and_array_in(self, port):
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""" Add pins for the write mask and array input """
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@ -488,7 +469,6 @@ class port_data(design.design):
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bank_wmask_name = "bank_wmask_{}".format(bit)
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self.copy_layout_pin(self.write_mask_and_array_inst, wmask_in_name, bank_wmask_name)
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def route_write_mask_and_array_to_write_driver(self,port):
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""" Routing of wdriver_sel_{} between write mask AND array and write driver array. Adds layout pin for write
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mask AND array output and via for write driver enable """
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@ -511,15 +491,15 @@ class port_data(design.design):
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while (wmask_out_pin.lx() + self.m2_pitch > inst2.get_pin("data_{0}".format(loc)).rx()):
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loc += 1
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length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch
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debug.check(loc<=self.num_wmasks,"Couldn't route the write mask select.")
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debug.check(loc<=self.num_wmasks,
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"Couldn't route the write mask select.")
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else:
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# Stride by the write size rather than finding the next pin to the right
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loc += self.write_size
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length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch
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length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch
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beg_pos = wmask_out_pin.center()
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middle_pos = vector(length,wmask_out_pin.cy())
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middle_pos = vector(length, wmask_out_pin.cy())
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end_pos = vector(length, wdriver_en_pin.cy())
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# Add via for the write driver array's enable input
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@ -529,7 +509,6 @@ class port_data(design.design):
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# Route between write mask AND array and write driver array
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self.add_wire(self.m1_stack, [beg_pos, middle_pos, end_pos])
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def route_column_mux_to_precharge_array(self, port):
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""" Routing of BL and BR between col mux and precharge array """
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@ -547,7 +526,6 @@ class port_data(design.design):
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num_bits=self.num_cols,
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inst2_start_bit=insn2_start_bit)
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def route_sense_amp_to_column_mux_or_precharge_array(self, port):
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""" Routing of BL and BR between sense_amp and column mux or precharge array """
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inst2 = self.sense_amp_array_inst
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@ -573,12 +551,9 @@ class port_data(design.design):
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num_bits=self.word_size,
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inst1_start_bit=start_bit)
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def route_write_driver_to_column_mux_or_precharge_array(self, port):
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""" Routing of BL and BR between sense_amp and column mux or precharge array """
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inst2 = self.write_driver_array_inst
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inst2_bl_name = inst2.mod.get_bl_name()
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inst2_br_name = inst2.mod.get_br_name()
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if self.col_addr_size>0:
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# Write driver is connected to the col mux
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@ -599,7 +574,6 @@ class port_data(design.design):
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inst1_bls_template=inst1_bls_templ,
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inst1_start_bit=start_bit)
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def route_write_driver_to_sense_amp(self, port):
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""" Routing of BL and BR between write driver and sense amp """
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@ -612,7 +586,6 @@ class port_data(design.design):
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inst2=inst2,
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num_bits=self.word_size)
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def route_bitline_pins(self):
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""" Add the bitline pins for the given port """
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@ -630,12 +603,15 @@ class port_data(design.design):
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for bit in range(self.num_cols):
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if self.precharge_array_inst:
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self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(bit+bit_offset), "bl_{}".format(bit))
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self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(bit+bit_offset), "br_{}".format(bit))
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self.copy_layout_pin(self.precharge_array_inst,
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"bl_{}".format(bit + bit_offset),
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"bl_{}".format(bit))
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self.copy_layout_pin(self.precharge_array_inst,
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"br_{}".format(bit + bit_offset),
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"br_{}".format(bit))
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else:
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debug.error("Didn't find precharge array.")
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def route_control_pins(self):
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""" Add the control pins: s_en, p_en_bar, w_en """
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if self.precharge_array_inst:
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@ -656,8 +632,6 @@ class port_data(design.design):
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if self.write_mask_and_array_inst:
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self.copy_layout_pin(self.write_mask_and_array_inst, "en", "w_en")
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def _group_bitline_instances(self, inst1, inst2, num_bits,
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inst1_bls_template,
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inst1_start_bit,
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@ -694,17 +668,16 @@ class port_data(design.design):
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Extracts bl/br pins from an InstanceGroup based on the bit modifier.
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"""
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full_bl_name = inst_group.bls_template.format(
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**{'inst' : inst_group.bl_name,
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'bit' : inst_group.start_bit + bit}
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)
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**{'inst': inst_group.bl_name,
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'bit': inst_group.start_bit + bit}
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)
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full_br_name = inst_group.bls_template.format(
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**{'inst' : inst_group.br_name,
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'bit' : inst_group.start_bit + bit}
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)
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**{'inst': inst_group.br_name,
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'bit': inst_group.start_bit + bit}
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)
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return (inst_group.inst.get_pin(full_bl_name),
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inst_group.inst.get_pin(full_br_name))
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def channel_route_bitlines(self, inst1, inst2, num_bits,
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inst1_bls_template="{inst}_{bit}",
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inst1_start_bit=0,
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@ -721,14 +694,13 @@ class port_data(design.design):
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# Channel route each mux separately since we don't minimize the number
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# of tracks in teh channel router yet. If we did, we could route all the bits at once!
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offset = bot_inst_group.inst.ul() + vector(0,self.m1_pitch)
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offset = bot_inst_group.inst.ul() + vector(0, self.m1_pitch)
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for bit in range(num_bits):
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bottom_names = self._get_bitline_pins(bot_inst_group, bit)
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top_names = self._get_bitline_pins(top_inst_group, bit)
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route_map = list(zip(bottom_names, top_names))
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self.create_horizontal_channel_route(route_map, offset, self.m1_stack)
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def connect_bitlines(self, inst1, inst2, num_bits,
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inst1_bls_template="{inst}_{bit}",
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@ -742,11 +714,9 @@ class port_data(design.design):
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"""
|
||||
|
||||
bot_inst_group, top_inst_group = self._group_bitline_instances(
|
||||
inst1, inst2, num_bits,
|
||||
inst1_bls_template, inst1_start_bit,
|
||||
inst2_bls_template, inst2_start_bit)
|
||||
bottom_inst = bot_inst_group.inst
|
||||
top_inst = top_inst_group.inst
|
||||
inst1, inst2, num_bits,
|
||||
inst1_bls_template, inst1_start_bit,
|
||||
inst2_bls_template, inst2_start_bit)
|
||||
|
||||
for col in range(num_bits):
|
||||
bot_bl_pin, bot_br_pin = self._get_bitline_pins(bot_inst_group, col)
|
||||
|
|
@ -754,11 +724,15 @@ class port_data(design.design):
|
|||
bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc()
|
||||
top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc()
|
||||
|
||||
yoffset = 0.5*(top_bl.y+bot_bl.y)
|
||||
self.add_path("m2",[bot_bl, vector(bot_bl.x,yoffset),
|
||||
vector(top_bl.x,yoffset), top_bl])
|
||||
self.add_path("m2",[bot_br, vector(bot_br.x,yoffset),
|
||||
vector(top_br.x,yoffset), top_br])
|
||||
yoffset = 0.5 * (top_bl.y + bot_bl.y)
|
||||
self.add_path("m2", [bot_bl,
|
||||
vector(bot_bl.x, yoffset),
|
||||
vector(top_bl.x, yoffset),
|
||||
top_bl])
|
||||
self.add_path("m2", [bot_br,
|
||||
vector(bot_br.x, yoffset),
|
||||
vector(top_br.x, yoffset),
|
||||
top_br])
|
||||
|
||||
def graph_exclude_precharge(self):
|
||||
"""Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
|
||||
|
|
|
|||
Loading…
Reference in New Issue