mirror of https://github.com/VLSIDA/OpenRAM.git
fix column decoder
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@ -21,14 +21,15 @@ class hierarchical_predecode(design.design):
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self.number_of_inputs = input_number
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b = factory.create(module_type="bitcell")
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if not height:
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self.cell_height = b.height
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self.column_decoder = False
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else:
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self.cell_height = height
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# If we are pitch matched to the bitcell, it's a predecoder
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# otherwise it's a column decoder (out of pgates)
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self.column_decoder = (height != b.height)
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# If we are pitch matched to the bitcell, it's a predecoder
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# otherwise it's a column decoder (out of pgates)
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self.column_decoder = (height != b.height)
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self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
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super().__init__(name)
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