mirror of https://github.com/VLSIDA/OpenRAM.git
Move write mask pin to left of cell to avoid sense amp
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@ -154,7 +154,6 @@ class write_driver_array(design.design):
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self.get_br_name() + "_{0}".format(index),
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self.en_name + "_{0}".format(i + offset), "vdd", "gnd"])
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def place_write_array(self):
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from tech import cell_properties
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if self.bitcell.width > self.driver.width:
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