mirror of https://github.com/VLSIDA/OpenRAM.git
Jog connection on M1 for bank select.
This commit is contained in:
mrg
parent
43dcf675a1
commit
32d190b8b1
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@ -45,11 +45,9 @@ class bank_select(design.design):
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self.height = max([x.uy() for x in self.inv_inst]) + self.m1_width
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self.width = max([x.rx() for x in self.inv_inst])
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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# Number of control lines in the bus
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@ -65,19 +63,18 @@ class bank_select(design.design):
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if (self.port == "rw") or (self.port == "r"):
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self.input_control_signals.append("s_en")
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# These will be outputs of the gaters if this is multibank
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self.control_signals = ["gated_"+str for str in self.input_control_signals]
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self.control_signals = ["gated_" + str for str in self.input_control_signals]
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self.add_pin_list(self.input_control_signals, "INPUT")
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self.add_pin("bank_sel")
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self.add_pin_list(self.control_signals, "OUTPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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""" Create modules for later instantiation """
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self.bitcell = factory.create(module_type="bitcell")
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height = self.bitcell.height + drc("poly_to_active")
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self.dff = factory.create(module_type="dff")
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height = self.dff.height + drc("poly_to_active")
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# 1x Inverter
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self.inv_sel = factory.create(module_type="pinv", height=height)
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@ -98,17 +95,15 @@ class bank_select(design.design):
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def calculate_module_offsets(self):
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self.xoffset_nand = self.inv4x.width + 2*self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_nor = self.inv4x.width + 2*self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_bank_sel_inv = 0
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self.xoffset_nand = self.inv4x.width + 2 * self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_nor = self.inv4x.width + 2 * self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_bank_sel_inv = 0
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self.xoffset_inputs = 0
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self.yoffset_maxpoint = self.num_control_lines * self.inv4x.height
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def create_instances(self):
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self.bank_sel_inv=self.add_inst(name="bank_sel_inv",
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self.bank_sel_inv=self.add_inst(name="bank_sel_inv",
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mod=self.inv_sel)
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self.connect_inst(["bank_sel", "bank_sel_bar", "vdd", "gnd"])
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@ -125,36 +120,36 @@ class bank_select(design.design):
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# (writes occur on clk low)
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if input_name in ("clk_buf"):
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self.logic_inst.append(self.add_inst(name=name_nor,
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mod=self.nor2))
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self.logic_inst.append(self.add_inst(name=name_nor,
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mod=self.nor2))
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self.connect_inst([input_name,
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"bank_sel_bar",
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gated_name+"_temp_bar",
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gated_name + "_temp_bar",
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"vdd",
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"gnd"])
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# They all get inverters on the output
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self.inv_inst.append(self.add_inst(name=name_inv,
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self.inv_inst.append(self.add_inst(name=name_inv,
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mod=self.inv4x_nor))
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self.connect_inst([gated_name+"_temp_bar",
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self.connect_inst([gated_name + "_temp_bar",
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gated_name,
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"vdd",
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"gnd"])
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# the rest are AND (nand2+inv) gates
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else:
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self.logic_inst.append(self.add_inst(name=name_nand,
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self.logic_inst.append(self.add_inst(name=name_nand,
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mod=self.nand2))
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self.connect_inst([input_name,
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"bank_sel",
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gated_name+"_temp_bar",
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gated_name + "_temp_bar",
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"vdd",
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"gnd"])
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# They all get inverters on the output
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self.inv_inst.append(self.add_inst(name=name_inv,
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self.inv_inst.append(self.add_inst(name=name_inv,
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mod=self.inv4x))
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self.connect_inst([gated_name+"_temp_bar",
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self.connect_inst([gated_name + "_temp_bar",
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gated_name,
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"vdd",
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"gnd"])
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@ -177,9 +172,9 @@ class bank_select(design.design):
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if i == 0:
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y_offset = 0
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else:
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y_offset = self.inv4x_nor.height + self.inv4x.height * (i-1)
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y_offset = self.inv4x_nor.height + self.inv4x.height * (i - 1)
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if i%2:
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if i % 2:
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y_offset += self.inv4x.height
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mirror = "MX"
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else:
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@ -200,7 +195,6 @@ class bank_select(design.design):
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# They all get inverters on the output
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inv_inst.place(offset=[logic_inst.rx(), y_offset],
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mirror=mirror)
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def route_instances(self):
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@ -222,57 +216,56 @@ class bank_select(design.design):
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end=bank_sel_pin_end)
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self.add_via_center(layers=self.m2_stack,
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offset=bank_sel_pin_end,
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directions=("H","H"))
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directions=("H", "H"))
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# bank_sel_bar is vertical wire
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bank_sel_bar_pin = self.bank_sel_inv.get_pin("Z")
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xoffset_bank_sel_bar = bank_sel_bar_pin.rx()
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self.add_label_pin(text="bank_sel_bar",
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layer="m2",
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offset=vector(xoffset_bank_sel_bar, 0),
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layer="m2",
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offset=vector(xoffset_bank_sel_bar, 0),
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height=self.inv4x.height)
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self.add_via_center(layers=self.m1_stack,
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offset=bank_sel_bar_pin.rc())
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for i in range(self.num_control_lines):
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logic_inst = self.logic_inst[i]
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inv_inst = self.inv_inst[i]
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input_name = self.input_control_signals[i]
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gated_name = self.control_signals[i]
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gated_name = self.control_signals[i]
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if input_name in ("clk_buf"):
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xoffset_bank_signal = xoffset_bank_sel_bar
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else:
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xoffset_bank_signal = xoffset_bank_sel
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# Connect the logic output to inverter input
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pre = logic_inst.get_pin("Z").lc()
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out_position = logic_inst.get_pin("Z").rc() + vector(0.5*self.m1_width,0)
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in_position = inv_inst.get_pin("A").lc() + vector(0.5*self.m1_width,0)
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post = inv_inst.get_pin("A").rc()
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self.add_path("m1", [pre, out_position, in_position, post])
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out_pin = logic_inst.get_pin("Z")
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out_pos = out_pin.rc()
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in_pin = inv_inst.get_pin("A")
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in_pos = in_pin.lc()
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mid1_pos = vector(0.5 * (out_pos.x + in_pos.x), out_pos.y)
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mid2_pos = vector(0.5 * (out_pos.x + in_pos.x), in_pos.y)
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self.add_path("m1", [out_pos, mid1_pos, mid2_pos, in_pos])
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# Connect the logic B input to bank_sel/bank_sel_bar
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logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1_via.height,0)
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# Connect the logic B input to bank_sel / bank_sel_bar
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logic_pos = logic_inst.get_pin("B").lc() - vector(0.5 * contact.m1_via.height, 0)
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input_pos = vector(xoffset_bank_signal, logic_pos.y)
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self.add_path("m2",[logic_pos, input_pos])
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self.add_path("m2", [logic_pos, input_pos])
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self.add_via_center(layers=self.m1_stack,
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offset=logic_pos,
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directions=("H","H"))
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directions=("H", "H"))
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# Connect the logic A input to the input pin
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logic_pos = logic_inst.get_pin("A").lc()
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input_pos = vector(0,logic_pos.y)
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input_pos = vector(0, logic_pos.y)
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self.add_via_center(layers=self.m1_stack,
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offset=logic_pos,
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directions=("H","H"))
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directions=("H", "H"))
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self.add_via_center(layers=self.m2_stack,
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offset=logic_pos,
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directions=("H","H"))
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directions=("H", "H"))
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self.add_layout_pin_segment_center(text=input_name,
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layer="m3",
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start=input_pos,
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@ -286,7 +279,6 @@ class bank_select(design.design):
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width=inv_inst.rx() - out_pin.lx(),
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height=out_pin.height())
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# Find the x offsets for where the vias/pins should be placed
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a_xoffset = self.logic_inst[0].lx()
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b_xoffset = self.inv_inst[0].lx()
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@ -294,7 +286,7 @@ class bank_select(design.design):
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# Route both supplies
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for n in ["vdd", "gnd"]:
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supply_pin = self.inv_inst[num].get_pin(n)
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supply_offset = supply_pin.ll().scale(0,1)
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supply_offset = supply_pin.ll().scale(0, 1)
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self.add_rect(layer="m1",
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offset=supply_offset,
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width=self.width)
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@ -304,10 +296,10 @@ class bank_select(design.design):
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pin_pos = vector(xoffset, supply_pin.cy())
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self.add_via_center(layers=self.m1_stack,
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offset=pin_pos,
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directions=("H","H"))
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directions=("H", "H"))
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self.add_via_center(layers=self.m2_stack,
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offset=pin_pos,
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directions=("H","H"))
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directions=("H", "H"))
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self.add_layout_pin_rect_center(text=n,
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layer="m3",
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offset=pin_pos)
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