Many edits.

Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.

compiler/base/custom_cell_properties.py

@@ -208,12 +208,18 @@ class cell_properties():
         self._bitcell_2port = _bitcell(["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"],
                                        ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"])
 
+        self._col_cap_1port = _bitcell(["bl", "br", "vdd"],
+                                       ["OUTPUT", "OUTPUT", "POWER"])
+
+        self._row_cap_1port = _bitcell(["wl", "gnd"],
+                                       ["INPUT", "POWER", "GROUND"])
+
         self._col_cap_2port = _bitcell(["bl0", "br0", "bl1", "br1", "vdd"],
                                        ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "POWER"])
 
         self._row_cap_2port = _bitcell(["wl0", "wl1", "gnd"],
                                        ["INPUT", "INPUT", "POWER", "GROUND"])
-
+        
     @property
     def ptx(self):
         return self._ptx
@@ -258,6 +264,14 @@ class cell_properties():
     def bitcell_2port(self):
         return self._bitcell_2port
 
+    @property
+    def col_cap_1port(self):
+        return self._col_cap_1port
+
+    @property
+    def row_cap_1port(self):
+        return self._row_cap_1port
+    
     @property
     def col_cap_2port(self):
         return self._col_cap_2port

compiler/base/hierarchy_spice.py

@@ -48,7 +48,7 @@ class spice():
         else:
             self.lvs_file = self.sp_file
         
-        self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
+        self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "BIAS", "POWER", "GROUND"]
         # Holds subckts/mods for this module
         self.mods = []
         # Holds the pins for this module (in order)

compiler/bitcells/bitcell_1port.py

@@ -22,38 +22,6 @@ class bitcell_1port(bitcell_base.bitcell_base):
         super().__init__(name, prop=props.bitcell_1port)
         debug.info(2, "Create bitcell")
 
-    def get_all_wl_names(self):
-        """ Creates a list of all wordline pin names """
-        row_pins = ["wl"]
-        return row_pins
-
-    def get_all_bitline_names(self):
-        """ Creates a list of all bitline pin names (both bl and br) """
-        return ["bl", "br"]
-
-    def get_all_bl_names(self):
-        """ Creates a list of all bl pins names """
-        return ["bl"]
-
-    def get_all_br_names(self):
-        """ Creates a list of all br pins names """
-        return ["br"]
-
-    def get_bl_name(self, port=0):
-        """Get bl name"""
-        debug.check(port == 0, "One port for bitcell only.")
-        return "bl"
-
-    def get_br_name(self, port=0):
-        """Get bl name"""
-        debug.check(port == 0, "One port for bitcell only.")
-        return "br"
-
-    def get_wl_name(self, port=0):
-        """Get wl name"""
-        debug.check(port == 0, "One port for bitcell only.")
-        return "wl"
-
     def build_graph(self, graph, inst_name, port_nets):
         """
         Adds edges based on inputs/outputs.
@@ -64,4 +32,4 @@ class bitcell_1port(bitcell_base.bitcell_base):
     def is_non_inverting(self):
         """Return input to output polarity for module"""
         
-        return False
+        return False

compiler/bitcells/bitcell_base.py

@@ -26,9 +26,7 @@ class bitcell_base(design.design):
             self.nets_match = self.do_nets_exist(prop.storage_nets)
             self.mirror = prop.mirror
             self.end_caps = prop.end_caps
-
-        self.supplies = ["vdd", "gnd"]
-        
+          
     def get_stage_effort(self, load):
         parasitic_delay = 1
         # This accounts for bitline being drained
@@ -172,3 +170,36 @@ class bitcell_base(design.design):
 
         """
         return
+    
+    def get_all_wl_names(self):
+        """ Creates a list of all wordline pin names """
+        row_pins = ["wl"]
+        return row_pins
+
+    def get_all_bitline_names(self):
+        """ Creates a list of all bitline pin names (both bl and br) """
+        return ["bl", "br"]
+
+    def get_all_bl_names(self):
+        """ Creates a list of all bl pins names """
+        return ["bl"]
+
+    def get_all_br_names(self):
+        """ Creates a list of all br pins names """
+        return ["br"]
+
+    def get_bl_name(self, port=0):
+        """Get bl name"""
+        debug.check(port == 0, "One port for bitcell only.")
+        return "bl"
+
+    def get_br_name(self, port=0):
+        """Get bl name"""
+        debug.check(port == 0, "One port for bitcell only.")
+        return "br"
+
+    def get_wl_name(self, port=0):
+        """Get wl name"""
+        debug.check(port == 0, "One port for bitcell only.")
+        return "wl"
+

compiler/modules/bitcell_base_array.py

@@ -35,11 +35,6 @@ class bitcell_base_array(design.design):
         self.rbl_wordline_names = [[] for port in self.all_ports]
         self.all_rbl_wordline_names = []
 
-        # The supply pin names
-        self.bitcell_supplies = self.cell.supplies
-        # If the technology needs renaming of the supplies
-        self.supplies = ["vdd", "gnd"]
-
     def create_all_bitline_names(self):
         for col in range(self.column_size):
             for port in self.all_ports:
@@ -63,8 +58,8 @@ class bitcell_base_array(design.design):
             self.add_pin(bl_name, "INOUT")
         for wl_name in self.get_wordline_names():
             self.add_pin(wl_name, "INPUT")
-        self.add_pin(self.supplies[0], "POWER")
-        self.add_pin(self.supplies[1], "GROUND")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def get_bitcell_pins(self, row, col):
         """
@@ -75,8 +70,8 @@ class bitcell_base_array(design.design):
         for port in self.all_ports:
             bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
         bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
-        bitcell_pins.append(self.bitcell_supplies[0])
-        bitcell_pins.append(self.bitcell_supplies[1])
+        bitcell_pins.append("vdd")
+        bitcell_pins.append("gnd")
 
         return bitcell_pins
 
@@ -166,8 +161,8 @@ class bitcell_base_array(design.design):
         for row in range(self.row_size):
             for col in range(self.column_size):
                 inst = self.cell_inst[row, col]
-                for (pin_name, new_name) in zip(self.bitcell_supplies, self.supplies):
-                    self.copy_layout_pin(inst, pin_name, new_name)
+                for pin_name in ["vdd", "gnd"]:
+                    self.copy_layout_pin(inst, pin_name)
 
     def _adjust_x_offset(self, xoffset, col, col_offset):
         tempx = xoffset

compiler/options.py

@@ -152,6 +152,8 @@ class options(optparse.Values):
     bitcell = "bitcell"
     buf_dec = "pbuf"
     column_mux_array = "column_mux_array"
+    col_cap = "col_cap"
+    col_cap_array = "col_cap_array"
     control_logic = "control_logic"
     decoder = "hierarchical_decoder"
     delay_chain = "delay_chain"
@@ -164,6 +166,8 @@ class options(optparse.Values):
     precharge_array = "precharge_array"
     ptx = "ptx"
     replica_bitline = "replica_bitline"
+    row_cap = "row_cap"
+    row_cap_array = "row_cap_array"
     sense_amp_array = "sense_amp_array"
     sense_amp = "sense_amp"
     tri_gate_array = "tri_gate_array"