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Change s8 to sky130

This commit is contained in:
mrg 2020-06-12 14:23:26 -07:00
parent 54e4d147f6
commit 443b8fbe23
21 changed files with 39 additions and 36 deletions
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2
compiler/base/hierarchy_layout.py
View File

@ -1348,7 +1348,7 @@ class layout():
offset=loc,
directions=directions)
# Hack for min area
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
width = round_to_grid(sqrt(drc["minarea_m3"]))
height = round_to_grid(drc["minarea_m3"]/width)
else:

2
compiler/characterizer/stimuli.py
View File

@ -254,7 +254,7 @@ class stimuli():
includes = self.device_models + [circuit]
self.sf.write("* {} process corner\n".format(self.process))
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
libraries = self.device_libraries
for item in list(libraries):
if os.path.isfile(item[0]):

4
compiler/custom/and2_dec.py
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@ -87,7 +87,7 @@ class and2_dec(design.design):
def route_supply_rails(self):
""" Add vdd/gnd rails to the top, (middle), and bottom. """
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
for name in ["vdd", "gnd"]:
for inst in [self.nand_inst, self.inv_inst]:
self.copy_layout_pin(inst, name)
@ -105,7 +105,7 @@ class and2_dec(design.design):
# nand Z to inv A
z1_pin = self.nand_inst.get_pin("Z")
a2_pin = self.inv_inst.get_pin("A")
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
mid1_point = vector(a2_pin.cx(), z1_pin.cy())
else:
mid1_point = vector(z1_pin.cx(), a2_pin.cy())

4
compiler/custom/and3_dec.py
View File

@ -86,7 +86,7 @@ class and3_dec(design.design):
def route_supply_rails(self):
""" Add vdd/gnd rails to the top, (middle), and bottom. """
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
for name in ["vdd", "gnd"]:
for inst in [self.nand_inst, self.inv_inst]:
self.copy_layout_pin(inst, name)
@ -104,7 +104,7 @@ class and3_dec(design.design):
# nand Z to inv A
z1_pin = self.nand_inst.get_pin("Z")
a2_pin = self.inv_inst.get_pin("A")
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
mid1_point = vector(a2_pin.cx(), z1_pin.cy())
else:
mid1_point = vector(z1_pin.cx(), a2_pin.cy())

4
compiler/custom/and4_dec.py
View File

@ -89,7 +89,7 @@ class and4_dec(design.design):
def route_supply_rails(self):
""" Add vdd/gnd rails to the top, (middle), and bottom. """
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
for name in ["vdd", "gnd"]:
for inst in [self.nand_inst, self.inv_inst]:
self.copy_layout_pin(inst, name)
@ -107,7 +107,7 @@ class and4_dec(design.design):
# nand Z to inv A
z1_pin = self.nand_inst.get_pin("Z")
a2_pin = self.inv_inst.get_pin("A")
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
mid1_point = vector(a2_pin.cx(), z1_pin.cy())
else:
mid1_point = vector(z1_pin.cx(), a2_pin.cy())

3
compiler/globals.py
View File

@ -99,6 +99,9 @@ def parse_args():
# Alias SCMOS to 180nm
if OPTS.tech_name == "scmos":
OPTS.tech_name = "scn4m_subm"
# Alias s8 to sky130
if OPTS.tech_name == "s8":
OPTS.tech_name = "sky130"
return (options, args)

2
compiler/modules/bitcell_base_array.py
View File

@ -102,7 +102,7 @@ class bitcell_base_array(design.design):
height=wl_pin.height())
# For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space
# Default uses prefered directions for each layer; this cell property is only currently used by s8 tech (03/20)
# Default uses prefered directions for each layer; this cell property is only currently used by sky130 tech (03/20)
try:
bitcell_power_pin_directions = cell_properties.bitcell_power_pin_directions
except AttributeError:

4
compiler/modules/hierarchical_decoder.py
View File

@ -159,7 +159,7 @@ class hierarchical_decoder(design.design):
# Inputs to cells are on input layer
# Outputs from cells are on output layer
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
self.bus_layer = "m1"
self.bus_directions = "nonpref"
self.bus_pitch = self.m1_pitch
@ -525,7 +525,7 @@ class hierarchical_decoder(design.design):
must-connects next level up.
"""
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
for n in ["vdd", "gnd"]:
pins = self.and_inst[0].get_pins(n)
for pin in pins:

8
compiler/modules/hierarchical_predecode.py
View File

@ -78,7 +78,7 @@ class hierarchical_predecode(design.design):
# Inputs to cells are on input layer
# Outputs from cells are on output layer
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
self.bus_layer = "m1"
self.bus_directions = None
self.bus_pitch = self.m1_pitch
@ -239,7 +239,7 @@ class hierarchical_predecode(design.design):
# add output so that it is just below the vdd or gnd rail
# since this is where the p/n devices are and there are no
# pins in the and gates.
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y)
self.add_path(self.output_layer, [inv_out_pos, rail_pos])
else:
@ -309,8 +309,8 @@ class hierarchical_predecode(design.design):
def route_vdd_gnd(self):
""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
# In s8, we use hand-made decoder cells with vertical power
if OPTS.tech_name == "s8":
# In sky130, we use hand-made decoder cells with vertical power
if OPTS.tech_name == "sky130":
for n in ["vdd", "gnd"]:
# This makes a wire from top to bottom for both inv and and gates
for i in [self.inv_inst, self.and_inst]:

4
compiler/modules/port_data.py
View File

@ -588,7 +588,7 @@ class port_data(design.design):
# This could be a channel route, but in some techs the bitlines
# are too close together.
elif OPTS.tech_name == "s8":
elif OPTS.tech_name == "sky130":
self.connect_bitlines(inst1=inst1,
inst1_bls_template=inst1_bls_templ,
inst2=inst2,
@ -646,7 +646,7 @@ class port_data(design.design):
# This could be a channel route, but in some techs the bitlines
# are too close together.
elif OPTS.tech_name == "s8":
elif OPTS.tech_name == "sky130":
self.connect_bitlines(inst1=inst1, inst2=inst2,
num_bits=self.word_size,
inst1_bls_template=inst1_bls_templ,

2
compiler/modules/wordline_driver_array.py
View File

@ -68,7 +68,7 @@ class wordline_driver_array(design.design):
Add a pin for each row of vdd/gnd which
are must-connects next level up.
"""
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
for name in ["vdd", "gnd"]:
supply_pins = self.wld_inst[0].get_pins(name)
for pin in supply_pins:

2
compiler/pgates/pgate.py
View File

@ -14,7 +14,7 @@ from tech import layer, drc
from vector import vector
from globals import OPTS
if(OPTS.tech_name == "s8"):
if(OPTS.tech_name == "sky130"):
from tech import nmos_bins, pmos_bins, accuracy_requirement

6
compiler/pgates/pinv.py
View File

@ -19,7 +19,7 @@ import logical_effort
from sram_factory import factory
from errors import drc_error
if(OPTS.tech_name == "s8"):
if(OPTS.tech_name == "sky130"):
from tech import nmos_bins, pmos_bins, accuracy_requirement
@ -88,7 +88,7 @@ class pinv(pgate.pgate):
self.tx_mults = 1
self.nmos_width = self.nmos_size * drc("minwidth_tx")
self.pmos_width = self.pmos_size * drc("minwidth_tx")
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
(self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
(self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)
return
@ -133,7 +133,7 @@ class pinv(pgate.pgate):
# Determine the number of mults for each to fit width
# into available space
if OPTS.tech_name != "s8":
if OPTS.tech_name != "sky130":
self.nmos_width = self.nmos_size * drc("minwidth_tx")
self.pmos_width = self.pmos_size * drc("minwidth_tx")
nmos_required_mults = max(int(ceil(self.nmos_width / nmos_height_available)), 1)

6
compiler/pgates/pinv_dec.py
View File

@ -13,7 +13,7 @@ from vector import vector
from globals import OPTS
from sram_factory import factory
if(OPTS.tech_name == "s8"):
if(OPTS.tech_name == "sky130"):
from tech import nmos_bins, pmos_bins, accuracy_requirement
@ -36,7 +36,7 @@ class pinv_dec(pinv.pinv):
# Inputs to cells are on input layer
# Outputs from cells are on output layer
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
self.supply_layer = "m1"
else:
self.supply_layer = "m2"
@ -53,7 +53,7 @@ class pinv_dec(pinv.pinv):
self.tx_mults = 1
self.nmos_width = self.nmos_size * drc("minwidth_tx")
self.pmos_width = self.pmos_size * drc("minwidth_tx")
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
(self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
(self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)
return

2
compiler/pgates/pnand2.py
View File

@ -37,7 +37,7 @@ class pnand2(pgate.pgate):
debug.check(size == 1, "Size 1 pnand2 is only supported now.")
self.tx_mults = 1
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
(self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
(self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)

2
compiler/pgates/pnand3.py
View File

@ -40,7 +40,7 @@ class pnand3(pgate.pgate):
"Size 1 pnand3 is only supported now.")
self.tx_mults = 1
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
(self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
(self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)

2
compiler/pgates/pnor2.py
View File

@ -37,7 +37,7 @@ class pnor2(pgate.pgate):
debug.check(size==1, "Size 1 pnor2 is only supported now.")
self.tx_mults = 1
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
(self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
(self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)

2
compiler/pgates/precharge.py
View File

@ -86,7 +86,7 @@ class precharge(design.design):
"""
Initializes the upper and lower pmos
"""
if(OPTS.tech_name == "s8"):
if(OPTS.tech_name == "sky130"):
(self.ptx_width, self.ptx_mults) = pgate.bin_width("pmos", self.ptx_width)
self.pmos = factory.create(module_type="ptx",
width=self.ptx_width,

8
compiler/pgates/ptx.py
View File

@ -126,8 +126,8 @@ class ptx(design.design):
# be decided in the layout later.
area_sd = 2.5 * self.poly_width * self.tx_width
perimeter_sd = 2 * self.poly_width + 2 * self.tx_width
if OPTS.tech_name == "s8":
# s8 technology is in microns, also needs mult parameter
if OPTS.tech_name == "sky130":
# sky130 technology is in microns, also needs mult parameter
(self.tx_width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width)
main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3}".format(spice[self.tx_type],
self.mults,
@ -149,8 +149,8 @@ class ptx(design.design):
# LVS lib is always in SI units
if os.path.exists(OPTS.openram_tech + "lvs_lib"):
if OPTS.tech_name == "s8":
# s8 requires mult parameter too
if OPTS.tech_name == "sky130":
# sky130 requires mult parameter too
self.lvs_device = "M{{0}} {{1}} {0} m={1} w={2} l={3} mult={1}".format(spice[self.tx_type],
self.mults,
self.tx_width,

4
compiler/pgates/wordline_driver.py
View File

@ -89,7 +89,7 @@ class wordline_driver(design.design):
def route_supply_rails(self):
""" Add vdd/gnd rails to the top, (middle), and bottom. """
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
for name in ["vdd", "gnd"]:
for inst in [self.nand_inst, self.driver_inst]:
self.copy_layout_pin(inst, name)
@ -110,7 +110,7 @@ class wordline_driver(design.design):
# nand Z to inv A
z1_pin = self.nand_inst.get_pin("Z")
a2_pin = self.driver_inst.get_pin("A")
if OPTS.tech_name == "s8":
if OPTS.tech_name == "sky130":
mid1_point = vector(a2_pin.cx(), z1_pin.cy())
else:
mid1_point = vector(z1_pin.cx(), a2_pin.cy())

2
compiler/verify/magic.py
View File

@ -68,7 +68,7 @@ def write_magic_script(cell_name, extract=False, final_verification=False):
if final_verification:
f.write(pre + "extract unique all\n".format(cell_name))
# Hack to work around unit scales in SkyWater
if OPTS.tech_name=="s8":
if OPTS.tech_name=="sky130":
f.write(pre + "extract style ngspice(si)\n")
f.write(pre + "extract\n".format(cell_name))
# f.write(pre + "ext2spice hierarchy on\n")