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Exclude bitcells in other local areas not of interest

This commit is contained in:
mrg 2020-09-29 12:15:42 -07:00
parent 0c280e062a
commit 449a4c2660
6 changed files with 55 additions and 18 deletions
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2
compiler/modules/bank.py
View File

@ -412,7 +412,7 @@ class bank(design.design):
def create_bitcell_array(self):
""" Creating Bitcell Array """
self.bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
self.bitcell_array_inst=self.add_inst(name="bitcell_array",
mod=self.bitcell_array)
# Arrays are always:
# word lines (bottom to top)

2
compiler/modules/bitcell_array.py
View File

@ -104,7 +104,7 @@ class bitcell_array(bitcell_base_array):
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c
return bl_wire
def graph_exclude_bits(self, targ_row, targ_col):
def graph_exclude_bits(self, targ_row=None, targ_col=None):
"""
Excludes bits in column from being added to graph except target
"""

33
compiler/modules/global_bitcell_array.py
View File

@ -272,15 +272,27 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
"""
Excludes bits in column from being added to graph except target
"""
# This must find which local array includes the specified column
# Find the summation of columns that is large and take the one before
for i, col in enumerate(self.col_offsets):
if col > targ_col:
break
else:
i = len(self.local_mods)
# This is the array with the column
local_array = self.local_mods[i - 1]
# We must also translate the global array column number to the local array column number
self.local_mods[i - 1].graph_exclude_bits(targ_row, targ_col - self.col_offsets[i - 1])
local_col = targ_col - self.col_offsets[i - 1]
for mod in self.local_mods:
if mod == local_array:
mod.graph_exclude_bits(targ_row, local_col)
else:
# Otherwise, we exclude ALL of the rows/columns
mod.graph_exclude_bits()
def graph_exclude_replica_col_bits(self):
"""
Exclude all but replica in every local array.
@ -300,8 +312,15 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
else:
# In this case, we it should be in the last bitcell array
i = len(self.col_offsets)
return self.local_mods[i - 1].get_cell_name(inst_name + '.x' + self.local_insts[i - 1].name, row, col)
# This is the local instance
local_inst = self.local_insts[i - 1]
# This is the array with the column
local_array = self.local_mods[i - 1]
# We must also translate the global array column number to the local array column number
local_col = col - self.col_offsets[i - 1]
return local_array.get_cell_name(inst_name + '.x' + local_inst.name, row, local_col)
def clear_exclude_bits(self):
"""
@ -309,3 +328,9 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
"""
for mod in self.local_mods:
mod.clear_exclude_bits()
def graph_exclude_dffs(self):
"""Exclude dffs from graph as they do not represent critical path"""
self.graph_inst_exclude.add(self.ctrl_dff_inst)

2
compiler/modules/local_bitcell_array.py
View File

@ -263,7 +263,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
offsets = [self.bitcell_array_inst.lx() + x for x in self.bitcell_array.get_column_offsets()]
return offsets
def graph_exclude_bits(self, targ_row, targ_col):
def graph_exclude_bits(self, targ_row=None, targ_col=None):
"""
Excludes bits in column from being added to graph except target
"""

2
compiler/modules/replica_bitcell_array.py
View File

@ -528,7 +528,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
return bl_wire
def graph_exclude_bits(self, targ_row, targ_col):
def graph_exclude_bits(self, targ_row=None, targ_col=None):
"""
Excludes bits in column from being added to graph except target
"""

32
compiler/sram/sram_1bank.py
View File

@ -542,7 +542,9 @@ class sram_1bank(sram_base):
[data_dff_clk_pos, mid_pos, clk_steiner_pos])
def route_control_logic(self):
""" Route the control logic pins that are not inputs """
"""
Route the control logic pins that are not inputs
"""
for port in self.all_ports:
for signal in self.control_logic_outputs[port]:
@ -567,7 +569,9 @@ class sram_1bank(sram_base):
offset=dest_pin.center())
def route_row_addr_dff(self):
""" Connect the output of the row flops to the bank pins """
"""
Connect the output of the row flops to the bank pins
"""
for port in self.all_ports:
for bit in range(self.row_addr_size):
flop_name = "dout_{}".format(bit)
@ -600,7 +604,9 @@ class sram_1bank(sram_base):
offset=pin.center())
def graph_exclude_data_dff(self):
"""Removes data dff and wmask dff (if applicable) from search graph. """
"""
Removes data dff and wmask dff (if applicable) from search graph.
"""
# Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay.
for inst in self.data_dff_insts:
self.graph_inst_exclude.add(inst)
@ -612,7 +618,9 @@ class sram_1bank(sram_base):
self.graph_inst_exclude.add(inst)
def graph_exclude_addr_dff(self):
"""Removes data dff from search graph. """
"""
Removes data dff from search graph.
"""
# Address is considered not part of the critical path, subjectively removed
for inst in self.row_addr_dff_insts:
self.graph_inst_exclude.add(inst)
@ -622,17 +630,21 @@ class sram_1bank(sram_base):
self.graph_inst_exclude.add(inst)
def graph_exclude_ctrl_dffs(self):
"""Exclude dffs for CSB, WEB, etc from graph"""
"""
Exclude dffs for CSB, WEB, etc from graph
"""
# Insts located in control logic, exclusion function called here
for inst in self.control_logic_insts:
inst.mod.graph_exclude_dffs()
def get_cell_name(self, inst_name, row, col):
"""Gets the spice name of the target bitcell."""
"""
Gets the spice name of the target bitcell.
"""
# Sanity check in case it was forgotten
if inst_name.find('x') != 0:
inst_name = 'x'+inst_name
return self.bank_inst.mod.get_cell_name(inst_name+'.x'+self.bank_inst.name, row, col)
if inst_name.find("x") != 0:
inst_name = "x" + inst_name
return self.bank_inst.mod.get_cell_name(inst_name + ".x" + self.bank_inst.name, row, col)
def get_bank_num(self, inst_name, row, col):
return 0;
return 0