mirror of https://github.com/VLSIDA/OpenRAM.git
Vdd/gnd via stacks now use perferred directions, added cell property to override
This commit is contained in:
Joey Kunzler
parent
1617840ed3
commit
d7529ce526
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@ -37,7 +37,7 @@ class layout():
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self.objs = [] # Holds all other objects (labels, geometries, etc)
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self.pin_map = {} # Holds name->pin_layout map for all pins
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self.visited = [] # List of modules we have already visited
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self.is_library_cell = False # Flag for library cells
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self.is_library_cell = False # Flag for library cells
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self.gds_read()
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try:
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from tech import power_grid
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@ -71,7 +71,7 @@ class layout():
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(inv_num + 1) * height - \
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(inv_num % 2) * drc["minwidth_m1"])
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y_dir = -1
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return (base_offset, y_dir)
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def find_lowest_coords(self):
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@ -90,7 +90,7 @@ class layout():
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lowesty2 = min(inst.by() for inst in self.insts)
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else:
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lowestx2 = lowesty2 = None
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if lowestx1 == None and lowestx2 == None:
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return None
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elif lowestx1 == None:
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@ -146,7 +146,7 @@ class layout():
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subcoord = inst.mod.find_highest_layer_coords(layer) + inst.offset
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highestx = max(highestx, subcoord.x)
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highesty = max(highesty, subcoord.y)
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return vector(highestx, highesty)
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def find_lowest_layer_coords(self, layer):
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@ -172,7 +172,7 @@ class layout():
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lowesty = min(lowesty, subcoord.y)
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return vector(lowestx, lowesty)
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def translate_all(self, offset):
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"""
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Translates all objects, instances, and pins by the given (x,y) offset
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@ -189,7 +189,7 @@ class layout():
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pin_list = self.pin_map[pin_name]
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for pin in pin_list:
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pin.rect = [pin.ll() - offset, pin.ur() - offset]
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def add_inst(self, name, mod, offset=[0, 0], mirror="R0", rotate=0):
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""" Adds an instance of a mod to this module """
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self.insts.append(geometry.instance(name, mod, offset, mirror, rotate))
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@ -204,7 +204,7 @@ class layout():
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if inst.name == name:
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return inst
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return None
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def add_rect(self, layer, offset, width=None, height=None):
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"""
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Adds a rectangle on a given layer,offset with width and height
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@ -260,7 +260,7 @@ class layout():
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start-offset,
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minwidth_layer,
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end.y-start.y)
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def get_pin(self, text):
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"""
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Return the pin or list of pins
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@ -275,7 +275,7 @@ class layout():
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except Exception:
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self.gds_write("missing_pin.gds")
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debug.error("No pin found with name {0} on {1}. Saved as missing_pin.gds.".format(text,self.name),-1)
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def get_pins(self, text):
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"""
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Return a pin list (instead of a single pin)
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@ -290,17 +290,17 @@ class layout():
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Return a pin list of all pins
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"""
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return self.pin_map.keys()
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def copy_layout_pin(self, instance, pin_name, new_name=""):
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"""
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Create a copied version of the layout pin at the current level.
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You can optionally rename the pin to a new name.
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"""
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pins = instance.get_pins(pin_name)
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debug.check(len(pins) > 0,
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"Could not find pin {}".format(pin_name))
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for pin in pins:
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if new_name == "":
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new_name = pin.name
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@ -317,7 +317,7 @@ class layout():
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"""
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for pin_name in self.pin_map.keys():
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self.copy_layout_pin(instance, pin_name, prefix+pin_name)
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def add_layout_pin_segment_center(self, text, layer, start, end):
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"""
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Creates a path like pin with center-line convention
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@ -325,9 +325,9 @@ class layout():
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debug.check(start.x == end.x or start.y == end.y,
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"Cannot have a non-manhatten layout pin.")
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minwidth_layer = drc["minwidth_{}".format(layer)]
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# one of these will be zero
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width = max(start.x, end.x) - min(start.x, end.x)
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height = max(start.y, end.y) - min(start.y, end.y)
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@ -341,7 +341,7 @@ class layout():
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# This makes sure it is long enough, but also it is not 0 width!
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height = max(minwidth_layer, height)
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width = max(minwidth_layer, width)
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return self.add_layout_pin(text,
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layer,
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ll_offset,
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@ -358,13 +358,13 @@ class layout():
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ll_offset = offset - vector(0.5 * width, 0.5 * height)
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return self.add_layout_pin(text, layer, ll_offset, width, height)
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def remove_layout_pin(self, text):
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"""
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Delete a labeled pin (or all pins of the same name)
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"""
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self.pin_map[text] = set()
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def add_layout_pin(self, text, layer, offset, width=None, height=None):
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"""
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Create a labeled pin
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@ -408,7 +408,7 @@ class layout():
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layer=layer,
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offset=offset + vector(0.5 * width,
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0.5 * height))
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def add_label(self, text, layer, offset=[0, 0], zoom=-1):
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"""Adds a text label on the given layer,offset, and zoom level"""
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# negative layers indicate "unused" layers in a given technology
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@ -447,7 +447,7 @@ class layout():
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layer_stack=layers,
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path=coordinates,
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layer_widths=layer_widths)
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def add_wire(self, layers, coordinates):
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"""Connects a routing path on given layer,coordinates,width.
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The layers are the (horizontal, via, vertical). """
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@ -462,14 +462,14 @@ class layout():
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""" Return the preferred routing directions """
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from tech import preferred_directions
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return preferred_directions[layer]
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def add_via(self, layers, offset, size=[1,1], directions=None, implant_type=None, well_type=None):
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""" Add a three layer via structure. """
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if not directions:
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directions = (self.get_preferred_direction(layers[0]),
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self.get_preferred_direction(layers[2]))
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from sram_factory import factory
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via = factory.create(module_type="contact",
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layer_stack=layers,
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@ -494,7 +494,7 @@ class layout():
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if not directions:
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directions = (self.get_preferred_direction(layers[0]),
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self.get_preferred_direction(layers[2]))
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from sram_factory import factory
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via = factory.create(module_type="contact",
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layer_stack=layers,
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@ -504,7 +504,7 @@ class layout():
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well_type=well_type)
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height = via.height
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width = via.width
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corrected_offset = offset + vector(-0.5 * width,
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-0.5 * height)
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@ -580,7 +580,7 @@ class layout():
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last_via=via,
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size=size)
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def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
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"""Adds a ptx module to the design."""
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import ptx
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@ -602,11 +602,11 @@ class layout():
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# This must be done for netlist only mode too
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if os.path.isfile(self.gds_file):
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self.is_library_cell = True
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if OPTS.netlist_only:
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self.gds = None
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return
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# open the gds file if it exists or else create a blank layout
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if os.path.isfile(self.gds_file):
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debug.info(3, "opening {}".format(self.gds_file))
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@ -662,7 +662,7 @@ class layout():
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height=height,
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center=False)
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debug.info(2, "Adding {0} boundary {1}".format(self.name, boundary))
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self.visited.append(self.name)
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def gds_write(self, gds_name):
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@ -681,10 +681,10 @@ class layout():
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# which may have been previously processed!
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# MRG: 10/4/18 We need to clear if we make changes and write a second GDS!
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self.clear_visited()
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# recursively create all the remaining objects
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self.gds_write_file(self.gds)
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# populates the xyTree data structure for gds
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# self.gds.prepareForWrite()
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writer.writeToFile(gds_name)
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@ -706,7 +706,7 @@ class layout():
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lpp = techlayer[layer]
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else:
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lpp = layer
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blockages = []
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for i in self.objs:
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blockages += i.get_blockages(lpp)
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@ -724,7 +724,7 @@ class layout():
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pin_names = copy.deepcopy(self.pins)
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if self.name.startswith("pmos") or self.name.startswith("nmos"):
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pin_names.remove("B")
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blockages = []
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for pin_name in pin_names:
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pin_list = self.get_pins(pin_name)
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@ -784,7 +784,7 @@ class layout():
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# half minwidth so we can return the center line offsets
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half_minwidth = 0.5 * drc["minwidth_{}".format(layer)]
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line_positions = {}
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if vertical:
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for i in range(len(names)):
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@ -829,7 +829,7 @@ class layout():
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layer_stack=("m1", "via1", "m2")):
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""" Vertical version of connect_bus. """
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self.connect_bus(mapping, inst, bus_offsets, layer_stack, False)
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def connect_bus(self, mapping, inst, bus_offsets, layer_stack, horizontal):
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"""
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Connect a mapping of pin -> name for a bus. This could be
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@ -842,7 +842,7 @@ class layout():
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route_layer = vertical_layer
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else:
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route_layer = horizontal_layer
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for (pin_name, bus_name) in mapping:
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pin = inst.get_pin(pin_name)
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pin_pos = pin.center()
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@ -854,7 +854,7 @@ class layout():
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else:
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# left/right then up/down
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mid_pos = vector(bus_pos.x, pin_pos.y)
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self.add_wire(layer_stack,
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[bus_pos, mid_pos, pin_pos])
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@ -865,7 +865,7 @@ class layout():
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offset=pin_pos)
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# FIXME: output pins tend to not be rotate,
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# but supply pins are. Make consistent?
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# We only need a via if they happened to align perfectly
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# so the add_wire didn't add a via
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if (horizontal and bus_pos.y == pin_pos.y) or (not horizontal and bus_pos.x == pin_pos.x):
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@ -899,7 +899,7 @@ class layout():
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self.m3_space)
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else:
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debug.error("Cannot find layer pitch.")
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def add_horizontal_trunk_route(self,
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pins,
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trunk_offset,
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@ -915,7 +915,7 @@ class layout():
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# if we are less than a pitch, just create a non-preferred layer jog
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if max_x-min_x <= pitch:
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half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)]
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# Add the horizontal trunk on the vertical layer!
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self.add_path(self.vertical_layer,
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[vector(min_x - half_layer_width, trunk_offset.y),
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@ -955,7 +955,7 @@ class layout():
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if max_y-min_y <= pitch:
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half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)]
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# Add the vertical trunk on the horizontal layer!
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self.add_path(self.horizontal_layer,
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[vector(trunk_offset.x, min_y - half_layer_width),
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@ -978,7 +978,7 @@ class layout():
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self.add_path(self.horizontal_layer, [pin.center(), mid])
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self.add_via_center(layers=layer_stack,
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offset=mid)
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def create_channel_route(self, netlist,
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offset,
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layer_stack,
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@ -996,7 +996,7 @@ class layout():
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Remove the pin from the graph and all conflicts
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"""
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g.pop(pin, None)
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# Remove the pin from all conflicts
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# FIXME: This is O(n^2), so maybe optimize it.
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for other_pin,conflicts in g.items():
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@ -1010,21 +1010,21 @@ class layout():
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Check all the pin pairs on two nets and return a pin
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overlap if any pin overlaps.
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"""
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for pin1 in net1:
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for pin2 in net2:
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if vcg_pin_overlap(pin1, pin2, vertical, pitch):
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return True
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return False
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def vcg_pin_overlap(pin1, pin2, vertical, pitch):
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""" Check for vertical or horizontal overlap of the two pins """
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# FIXME: If the pins are not in a row, this may break.
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# However, a top pin shouldn't overlap another top pin,
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# for example, so the
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# extra comparison *shouldn't* matter.
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# Pin 1 must be in the "BOTTOM" set
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x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x-pin2.center().x)<pitch
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@ -1049,7 +1049,7 @@ class layout():
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# too if we want to minimize the
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# number of tracks!
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# hcg = {}
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# Initialize the vertical conflict graph (vcg)
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# and make a list of all pins
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vcg = collections.OrderedDict()
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@ -1084,7 +1084,7 @@ class layout():
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vertical,
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self.horizontal_pitch):
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vcg[net_name2].append(net_name1)
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# list of routes to do
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while vcg:
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# from pprint import pformat
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@ -1105,7 +1105,7 @@ class layout():
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# Remove the net from other constriants in the VCG
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vcg = remove_net_from_graph(net_name, vcg)
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# Add the trunk routes from the bottom up for
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# horizontal or the left to right for vertical
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if vertical:
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@ -1137,7 +1137,7 @@ class layout():
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""" Add boundary for debugging dimensions """
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if OPTS.netlist_only:
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return
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if "stdc" in techlayer.keys():
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boundary_layer = "stdc"
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else:
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@ -1152,7 +1152,7 @@ class layout():
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offset=ll,
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height=ur.y-ll.y,
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width=ur.x-ll.x)
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def add_enclosure(self, insts, layer="nwell"):
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""" Add a layer that surrounds the given instances. Useful
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for creating wells, for example. Doesn't check for minimum widths or
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@ -1193,19 +1193,25 @@ class layout():
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"supply router."
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.format(name,inst.name,self.pwr_grid_layer))
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def add_power_pin(self, name, loc, size=[1, 1], vertical=False, start_layer="m1"):
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"""
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Add a single power pin from the lowest power_grid layer down to M1 at
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the given center location. The starting layer is specified to determine
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which vias are needed.
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"""
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# Force vdd/gnd via stack to be vertically or horizontally oriented
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# Default: None, uses prefered metal directions
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if vertical:
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direction = ("V", "V")
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else:
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elif not vertical and vertical is not None:
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direction = ("H", "H")
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else:
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direction = None
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via = self.add_via_stack_center(from_layer=start_layer,
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to_layer=self.pwr_grid_layer,
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size=size,
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@ -1222,7 +1228,7 @@ class layout():
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offset=loc,
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width=via.width,
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height=via.height)
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def add_power_ring(self, bbox):
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"""
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Create vdd and gnd power rings around an area of the bounding box
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@ -1287,7 +1293,7 @@ class layout():
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offset=offset,
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width=width,
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height=self.supply_rail_width)
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# TOP horizontal rails
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offset = vector(ll.x, ur.y) + vector(-2 * self.supply_rail_pitch,
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0)
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@ -1328,7 +1334,7 @@ class layout():
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else:
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self.supply_vias -= 1
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break
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via_points = [vector(self.left_gnd_x_center, self.bottom_gnd_y_center),
|
||||
vector(self.left_gnd_x_center, self.top_gnd_y_center),
|
||||
vector(self.right_gnd_x_center, self.bottom_gnd_y_center),
|
||||
|
|
@ -1337,7 +1343,7 @@ class layout():
|
|||
vector(self.left_vdd_x_center, self.top_vdd_y_center),
|
||||
vector(self.right_vdd_x_center, self.bottom_vdd_y_center),
|
||||
vector(self.right_vdd_x_center, self.top_vdd_y_center)]
|
||||
|
||||
|
||||
for pt in via_points:
|
||||
self.add_via_center(layers=self.m1_stack,
|
||||
offset=pt,
|
||||
|
|
@ -1390,4 +1396,3 @@ class layout():
|
|||
debug.info(0, "name={0} : mod={1} : offset={2}".format(inst.name,
|
||||
inst.mod.name,
|
||||
inst.offset))
|
||||
|
||||
|
|
|
|||
|
|
@ -101,13 +101,20 @@ class bitcell_base_array(design.design):
|
|||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# For every second row and column, add a via for gnd and vdd
|
||||
# For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space
|
||||
# Default uses prefered directions for each layer; this cell property is only currently used by s8 tech (03/20)
|
||||
try:
|
||||
force_power_pins_vertical = cell_properties.bitcell_force_power_pins_vertical
|
||||
except AttributeError:
|
||||
force_power_pins_vertical = None
|
||||
|
||||
# Add vdd/gnd via stacks
|
||||
for row in range(self.row_size):
|
||||
for col in range(self.column_size):
|
||||
inst = self.cell_inst[row,col]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
for pin in inst.get_pins(pin_name):
|
||||
self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
|
||||
self.add_power_pin(name=pin_name, loc=pin.center(), vertical=force_power_pins_vertical, start_layer=pin.layer)
|
||||
|
||||
def _adjust_x_offset(self, xoffset, col, col_offset):
|
||||
tempx = xoffset
|
||||
|
|
|
|||
Loading…
Reference in New Issue