mirror of https://github.com/VLSIDA/OpenRAM.git
Add wells to driver stages. Remove unnecessary height/center in control logic.
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@ -338,8 +338,6 @@ class control_logic(design.design):
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_wen_row(row)
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height = self.w_en_gate_inst.uy()
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control_center_y = self.w_en_gate_inst.uy()
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row += 1
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self.place_pen_row(row)
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row += 1
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@ -87,13 +87,11 @@ class pdriver(pgate.pgate):
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def add_modules(self):
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self.inv_list = []
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add_well = self.add_wells
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for size in self.size_list:
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temp_inv = factory.create(module_type="pinv",
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size=size,
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height=self.height,
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add_wells=add_well)
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add_well=False
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add_wells=self.add_wells)
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self.inv_list.append(temp_inv)
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self.add_mod(temp_inv)
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