mirror of https://github.com/VLSIDA/OpenRAM.git
port_data: Refactor channel_route/connect_bitlines()
both functions share a lot of code and are passing around a lot of data
under similar names (inst1, inst1_start_bit, inst1_bl_name, ...). Thus
we group all these elements in a named tuple to ease passing around
these elements.
All callers of channel_route/connect_bitlines() either pass in the bl/br
names or rely on "br_{}"/"bl_{}" as defaults. These hard coded values
should be determined by the instances. Thus we get the bitline names
based on the instances passed in. The callers only provide a template
string, to take care of the case that bitlines are called "bl_out_{}".
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann
parent
5e1f64c8f9
commit
656fdd1008
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@ -8,6 +8,7 @@ from tech import drc, parameter
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import debug
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import design
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from sram_factory import factory
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from collections import namedtuple
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from vector import vector
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from globals import OPTS
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@ -535,13 +536,16 @@ class port_data(design.design):
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# Only do this if we have a column mux!
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if self.col_addr_size==0:
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return
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inst1 = self.column_mux_array_inst
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inst2 = self.precharge_array_inst
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if self.port==0:
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self.connect_bitlines(inst1, inst2, self.num_cols, inst2_start_bit=1)
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else:
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self.connect_bitlines(inst1, inst2, self.num_cols)
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insn2_start_bit = 1 if self.port == 0 else 0
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self.connect_bitlines(inst1=inst1,
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inst2=inst2,
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num_bits=self.num_cols,
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inst2_start_bit=insn2_start_bit)
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def route_sense_amp_to_column_mux_or_precharge_array(self, port):
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@ -551,46 +555,49 @@ class port_data(design.design):
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if self.col_addr_size>0:
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# Sense amp is connected to the col mux
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inst1 = self.column_mux_array_inst
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inst1_bl_name = "bl_out_{}"
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inst1_br_name = "br_out_{}"
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inst1_bls_templ = "{inst}_out_{bit}"
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start_bit = 0
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else:
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# Sense amp is directly connected to the precharge array
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inst1 = self.precharge_array_inst
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inst1_bl_name = "bl_{}"
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inst1_br_name = "br_{}"
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inst1_bls_templ="{inst}_{bit}"
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if self.port==0:
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start_bit=1
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else:
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start_bit=0
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self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
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inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst1_start_bit=start_bit)
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self.channel_route_bitlines(inst1=inst1,
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inst1_bls_template=inst1_bls_templ,
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inst2=inst2,
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num_bits=self.word_size,
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inst1_start_bit=start_bit)
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def route_write_driver_to_column_mux_or_precharge_array(self, port):
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""" Routing of BL and BR between sense_amp and column mux or precharge array """
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inst2 = self.write_driver_array_inst
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inst2_bl_name = inst2.mod.get_bl_name()
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inst2_br_name = inst2.mod.get_br_name()
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if self.col_addr_size>0:
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# Write driver is connected to the col mux
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inst1 = self.column_mux_array_inst
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inst1_bl_name = "bl_out_{}"
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inst1_br_name = "br_out_{}"
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inst1_bls_templ = "{inst}_out_{bit}"
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start_bit = 0
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else:
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# Sense amp is directly connected to the precharge array
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inst1 = self.precharge_array_inst
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inst1_bl_name = "bl_{}"
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inst1_br_name = "br_{}"
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inst1_bls_templ="{inst}_{bit}"
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if self.port==0:
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start_bit=1
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else:
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start_bit=0
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self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
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inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst1_start_bit=start_bit)
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self.channel_route_bitlines(inst1=inst1, inst2=inst2,
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num_bits=self.word_size,
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inst1_bls_template=inst1_bls_templ,
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inst1_start_bit=start_bit)
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def route_write_driver_to_sense_amp(self, port):
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@ -601,7 +608,9 @@ class port_data(design.design):
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# These should be pitch matched in the cell library,
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# but just in case, do a channel route.
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self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size)
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self.channel_route_bitlines(inst1=inst1,
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inst2=inst2,
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num_bits=self.word_size)
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def route_bitline_pins(self):
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@ -647,64 +656,108 @@ class port_data(design.design):
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if self.write_mask_and_array_inst:
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self.copy_layout_pin(self.write_mask_and_array_inst, "en", "w_en")
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def channel_route_bitlines(self, inst1, inst2, num_bits,
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inst1_bl_name="bl_{}", inst1_br_name="br_{}", inst1_start_bit=0,
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inst2_bl_name="bl_{}", inst2_br_name="br_{}", inst2_start_bit=0):
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def _group_bitline_instances(self, inst1, inst2, num_bits,
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inst1_bls_template,
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inst1_start_bit,
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inst2_bls_template,
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inst2_start_bit):
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"""
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Route the bl and br of two modules using the channel router.
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Groups all the parameters into a named tuple and seperates them into
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top and bottom instances.
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"""
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inst_group = namedtuple('InstanceGroup', ('inst', 'bls_template',
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'bl_name', 'br_name', 'start_bit'))
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inst1_group = inst_group(inst1, inst1_bls_template,
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inst1.mod.get_bl_name(),
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inst1.mod.get_br_name(),
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inst1_start_bit)
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inst2_group = inst_group(inst2, inst2_bls_template,
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inst2.mod.get_bl_name(),
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inst2.mod.get_br_name(),
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inst2_start_bit)
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# determine top and bottom automatically.
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# since they don't overlap, we can just check the bottom y coordinate.
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if inst1.by() < inst2.by():
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(bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit)
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(top_inst, top_bl_name, top_br_name, top_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit)
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bot_inst_group = inst1_group
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top_inst_group = inst2_group
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else:
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(bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit)
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(top_inst, top_bl_name, top_br_name, top_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit)
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bot_inst_group = inst2_group
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top_inst_group = inst1_group
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return (bot_inst_group, top_inst_group)
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def _get_bitline_pins(self, inst_group, bit):
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"""
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Extracts bl/br pins from an InstanceGroup based on the bit modifier.
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"""
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full_bl_name = inst_group.bls_template.format(
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**{'inst' : inst_group.bl_name,
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'bit' : inst_group.start_bit + bit}
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)
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full_br_name = inst_group.bls_template.format(
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**{'inst' : inst_group.br_name,
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'bit' : inst_group.start_bit + bit}
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)
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return (inst_group.inst.get_pin(full_bl_name),
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inst_group.inst.get_pin(full_br_name))
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def channel_route_bitlines(self, inst1, inst2, num_bits,
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inst1_bls_template="{inst}_{bit}",
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inst1_start_bit=0,
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inst2_bls_template="{inst}_{bit}",
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inst2_start_bit=0):
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"""
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Route the bl and br of two modules using the channel router.
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"""
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bot_inst_group, top_inst_group = self._group_bitline_instances(
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inst1, inst2, num_bits,
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inst1_bls_template, inst1_start_bit,
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inst2_bls_template, inst2_start_bit)
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# Channel route each mux separately since we don't minimize the number
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# of tracks in teh channel router yet. If we did, we could route all the bits at once!
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offset = bottom_inst.ul() + vector(0,self.m1_pitch)
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offset = bot_inst_group.inst.ul() + vector(0,self.m1_pitch)
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for bit in range(num_bits):
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bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit+bottom_start_bit)), bottom_inst.get_pin(bottom_br_name.format(bit+bottom_start_bit))]
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top_names = [top_inst.get_pin(top_bl_name.format(bit+top_start_bit)), top_inst.get_pin(top_br_name.format(bit+top_start_bit))]
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bottom_names = self._get_bitline_pins(bot_inst_group, bit)
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top_names = self._get_bitline_pins(top_inst_group, bit)
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route_map = list(zip(bottom_names, top_names))
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self.create_horizontal_channel_route(route_map, offset, self.m1_stack)
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def connect_bitlines(self, inst1, inst2, num_bits,
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inst1_bl_name="bl_{}", inst1_br_name="br_{}", inst1_start_bit=0,
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inst2_bl_name="bl_{}", inst2_br_name="br_{}", inst2_start_bit=0):
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inst1_bls_template="{inst}_{bit}",
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inst1_start_bit=0,
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inst2_bls_template="{inst}_{bit}",
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inst2_start_bit=0):
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"""
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Connect the bl and br of two modules.
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This assumes that they have sufficient space to create a jog
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in the middle between the two modules (if needed).
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"""
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# determine top and bottom automatically.
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# since they don't overlap, we can just check the bottom y coordinate.
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if inst1.by() < inst2.by():
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(bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit)
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(top_inst, top_bl_name, top_br_name, top_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit)
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else:
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(bottom_inst, bottom_bl_name, bottom_br_name, bottom_start_bit) = (inst2, inst2_bl_name, inst2_br_name, inst2_start_bit)
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(top_inst, top_bl_name, top_br_name, top_start_bit) = (inst1, inst1_bl_name, inst1_br_name, inst1_start_bit)
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bot_inst_group, top_inst_group = self._group_bitline_instances(
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inst1, inst2, num_bits,
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inst1_bls_template, inst1_start_bit,
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inst2_bls_template, inst2_start_bit)
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bottom_inst = bot_inst_group.inst
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top_inst = top_inst_group.inst
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for col in range(num_bits):
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bottom_bl = bottom_inst.get_pin(bottom_bl_name.format(col+bottom_start_bit)).uc()
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bottom_br = bottom_inst.get_pin(bottom_br_name.format(col+bottom_start_bit)).uc()
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top_bl = top_inst.get_pin(top_bl_name.format(col+top_start_bit)).bc()
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top_br = top_inst.get_pin(top_br_name.format(col+top_start_bit)).bc()
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bot_bl_pin, bot_br_pin = self._get_bitline_pins(bot_inst_group, col)
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top_bl_pin, top_br_pin = self._get_bitline_pins(top_inst_group, col)
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bot_bl, bot_br = bot_bl_pin.uc(), bot_br_pin.uc()
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top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc()
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yoffset = 0.5*(top_bl.y+bottom_bl.y)
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self.add_path("m2",[bottom_bl, vector(bottom_bl.x,yoffset),
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yoffset = 0.5*(top_bl.y+bot_bl.y)
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self.add_path("m2",[bot_bl, vector(bot_bl.x,yoffset),
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vector(top_bl.x,yoffset), top_bl])
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self.add_path("m2",[bottom_br, vector(bottom_br.x,yoffset),
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self.add_path("m2",[bot_br, vector(bot_br.x,yoffset),
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vector(top_br.x,yoffset), top_br])
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def graph_exclude_precharge(self):
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