bank: Connect instances by their individual bl/br names

each module should be able to state how their bl/br lines are named. Here we
always connect port_data with the bitcell_array, so port_data needs function
that return the names of bl/br.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

compiler/modules/bank.py

@@ -679,9 +679,13 @@ class bank(design.design):
         inst1 = self.bitcell_array_inst
         inst1_bl_name = self.bl_names[port]+"_{}"
         inst1_br_name = self.br_names[port]+"_{}"
+
+        inst2_bl_name = inst2.mod.get_bl_names()+"_{}"
+        inst2_br_name = inst2.mod.get_br_names()+"_{}"
         
         self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols,
-                              inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
+                              inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name,
+                              inst2_bl_name=inst2_bl_name, inst2_br_name=inst2_br_name)
 
         # Connect the replica bitlines
         rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
@@ -786,8 +790,8 @@ class bank(design.design):
         
 
     def connect_bitlines(self, inst1, inst2, num_bits,
-                         inst1_bl_name="bl_{}", inst1_br_name="br_{}",
-                         inst2_bl_name="bl_{}", inst2_br_name="br_{}"):
+                         inst1_bl_name, inst1_br_name,
+                         inst2_bl_name, inst2_br_name):
         """
         Connect the bl and br of two modules.
         """

compiler/modules/port_data.py

@@ -38,6 +38,15 @@ class port_data(design.design):
             self.create_layout()
             self.add_boundary()
 
+    def get_bl_names(self):
+        # bl lines are connect from the precharger
+        return self.precharge.get_bl_names()
+
+    def get_br_names(self):
+        # br lines are connect from the precharger
+        return self.precharge.get_br_names()
+
+
 
     def create_netlist(self):
         self.precompute_constants()
@@ -221,6 +230,11 @@ class port_data(design.design):
         self.bl_names = self.bitcell.get_all_bl_names()
         self.br_names = self.bitcell.get_all_br_names()
         self.wl_names = self.bitcell.get_all_wl_names()
+        # used for bl/br names
+        self.precharge = factory.create(module_type="precharge",
+                                        bitcell_bl = self.bl_names[0],
+                                        bitcell_br = self.br_names[0])
+
 
     def create_precharge_array(self):
         """ Creating Precharge """

compiler/pgates/precharge.py

@@ -38,6 +38,12 @@ class precharge(design.design):
             self.create_layout()
             self.DRC_LVS()
 
+    def get_bl_names(self):
+        return "bl"
+
+    def get_br_names(self):
+        return "br"
+
     def create_netlist(self):
         self.add_pins()
         self.add_ptx()