mirror of https://github.com/VLSIDA/OpenRAM.git
Use pin of pgate to figure out supply layer.
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@ -119,7 +119,7 @@ class control_logic(design.design):
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# We will use the maximum since this same value is used to size the wl_en
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# and the p_en_bar drivers
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max_fanout = max(self.num_rows, self.num_cols)
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# max_fanout = max(self.num_rows, self.num_cols)
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# wl_en drives every row in the bank
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self.wl_en_driver = factory.create(module_type="pdriver",
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@ -162,6 +162,8 @@ class control_logic(design.design):
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self.delay_chain=factory.create(module_type="delay_chain",
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fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ])
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self.add_mod(self.delay_chain)
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self.supply_layer = self.inv.get_pin("vdd").layer
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def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout):
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"""Determine the size of the delay chain used for the Sense Amp Enable using path delays"""
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@ -721,27 +723,23 @@ class control_logic(design.design):
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def route_supply(self):
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""" Add vdd and gnd to the instance cells """
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if OPTS.tech_name == "sky130":
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supply_layer = "li"
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else:
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supply_layer = "m1"
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max_row_x_loc = max([inst.rx() for inst in self.row_end_inst])
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for inst in self.row_end_inst:
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pins = inst.get_pins("vdd")
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for pin in pins:
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if pin.layer == supply_layer:
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if pin.layer == self.supply_layer:
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row_loc = pin.rc()
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pin_loc = vector(max_row_x_loc, pin.rc().y)
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self.add_power_pin("vdd", pin_loc, start_layer=pin.layer)
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self.add_path(supply_layer, [row_loc, pin_loc])
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self.add_path(self.supply_layer, [row_loc, pin_loc])
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pins = inst.get_pins("gnd")
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for pin in pins:
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if pin.layer == supply_layer:
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if pin.layer == self.supply_layer:
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row_loc = pin.rc()
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pin_loc = vector(max_row_x_loc, pin.rc().y)
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self.add_power_pin("gnd", pin_loc, start_layer=pin.layer)
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self.add_path(supply_layer, [row_loc, pin_loc])
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self.add_path(self.supply_layer, [row_loc, pin_loc])
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self.copy_layout_pin(self.delay_inst, "gnd")
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self.copy_layout_pin(self.delay_inst, "vdd")
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