Update riscv unit test

compiler/modules/bank.py

@@ -374,15 +374,15 @@ class bank(design.design):
                                                     port=port))
             self.add_mod(self.port_address[port])
 
+        total_cols = self.num_cols + self.num_spare_cols
+        
         try:
             local_array_size = OPTS.local_array_size
         except AttributeError:
-            #local_array_size = ceil(sqrt(self.num_cols + self.num_spare_cols))
-            local_array_size = ceil(sqrt(self.num_cols + self.num_spare_cols))
+            local_array_size = 0
             
         if local_array_size > 0:
             # Find the even multiple that satisfies the fanout with equal sized local arrays
-            total_cols = self.num_cols + self.num_spare_cols
             num_lb = floor(total_cols / local_array_size)
             final_size = total_cols - num_lb * local_array_size
             cols = [local_array_size] * (num_lb - 1)
@@ -393,7 +393,7 @@ class bank(design.design):
                                                 rows=self.num_rows)
         else:
             self.bitcell_array = factory.create(module_type="replica_bitcell_array",
-                                                cols=self.num_cols + self.num_spare_cols,
+                                                cols=total_cols,
                                                 rows=self.num_rows)
         self.add_mod(self.bitcell_array)
 

compiler/tests/50_riscv_func_test.py

@@ -22,13 +22,15 @@ class riscv_func_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-        OPTS.analytical_delay = False
-        OPTS.netlist_only = True
-        OPTS.trim_netlist = False
+        
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
         globals.setup_bitcell()
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+        OPTS.local_array_size = 16
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload

compiler/tests/50_riscv_phys_test.py

@@ -28,8 +28,9 @@ class riscv_phys_test(openram_test):
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
         globals.setup_bitcell()
-        OPTS.route_supplies=False
-        OPTS.perimeter_pins=False
+        OPTS.route_supplies = False
+        OPTS.perimeter_pins = False
+        OPTS.local_array_size = 16
         
         c = sram_config(word_size=32,
                         write_size=8,