Changed layout input names of s_en AND gate to match the schematic

2020-02-19 23:32:11 -08:00 · 2020-02-19 23:32:11 -08:00 · c1cb6bf512
parent df2f981a34
commit c1cb6bf512
1 changed files with 1 additions and 1 deletions
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@ -670,7 +670,7 @@ class control_logic(design.design):
        if self.port_type=="rw":
            input_name = "we_bar"
        else:
-            input_name = "cs_bar"
+            input_name = "cs"
            
        sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name])
        self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)