mirror of https://github.com/VLSIDA/OpenRAM.git
Conditional well spacing
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parent
94eb2afa36
commit
9d2902de9e
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@ -7,13 +7,13 @@
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#
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import debug
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import design
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from tech import drc,parameter
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from tech import parameter
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from tech import cell_properties as props
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from math import log
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from vector import vector
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from globals import OPTS
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from sram_factory import factory
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class dff_buf(design.design):
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"""
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This is a simple buffered DFF. The output is buffered
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@ -107,13 +107,23 @@ class dff_buf(design.design):
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self.dff_inst.place(vector(0,0))
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# Add INV1 to the right
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well_spacing = max(self.nwell_space,
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self.pwell_space,
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self.pwell_to_nwell)
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self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing + self.well_extend_active,0))
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well_spacing = 0
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try:
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well_spacing = max(well_spacing, self.nwell_space)
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except AttributeError:
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pass
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try:
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well_spacing = max(well_spacing, self.pwell_space)
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except AttributeError:
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pass
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try:
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well_spacing = max(well_spacing, self.pwell_to_nwell)
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except AttributeError:
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pass
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self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing + self.well_extend_active, 0))
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# Add INV2 to the right
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self.inv2_inst.place(vector(self.inv1_inst.rx(),0))
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self.inv2_inst.place(vector(self.inv1_inst.rx(), 0))
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def route_wires(self):
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# Route dff q to inv1 a
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