mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed offset in port_data
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2fcecb7227
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@ -732,8 +732,8 @@ class port_data(design.design):
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top_bl, top_br = top_bl_pin.bc(), top_br_pin.bc()
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layer_pitch = getattr(self, "{}_pitch".format(top_bl_pin.layer))
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self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V", top_bl_pin.by() - layer_pitch)
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self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V", top_bl_pin.by() - 2 * layer_pitch)
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self.add_zjog(bot_bl_pin.layer, bot_bl, top_bl, "V", fixed_offset=top_bl_pin.by() - layer_pitch)
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self.add_zjog(bot_br_pin.layer, bot_br, top_br, "V", fixed_offset=top_bl_pin.by() - 2 * layer_pitch)
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def graph_exclude_precharge(self):
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"""Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
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