mirror of https://github.com/VLSIDA/OpenRAM.git
Fix missing via for global wordlines.
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f45efe3db6
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@ -217,17 +217,20 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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y_offset += global_wl_pitch_factor * global_wl_pitch
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mid = vector(in_pin.cx(), y_offset)
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# A short jog to the global line
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self.add_via_stack_center(from_layer=in_pin.layer,
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to_layer=local_wl_layer,
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offset=in_pin.center(),
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min_area=True)
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self.add_path(local_wl_layer, [in_pin.center(), mid])
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self.add_via_stack_center(from_layer=local_wl_layer,
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to_layer=global_wl_layer,
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offset=mid,
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min_area=True)
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# Add the global WL pin
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self.add_layout_pin_rect_center(text=wl_name,
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layer=global_wl_layer,
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offset=mid)
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self.add_path(local_wl_layer, [in_pin.center(), mid])
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self.add_via_stack_center(from_layer=in_pin.layer,
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to_layer=local_wl_layer,
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offset=mid,
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min_area=True)
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# Route the buffers
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for port in self.all_ports:
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driver_outputs = self.driver_wordline_outputs[port]
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