mirror of https://github.com/VLSIDA/OpenRAM.git
s8 col mux array
This commit is contained in:
Joey Kunzler
parent
60ba2c1aa5
commit
fed1c0bbe1
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@ -5,17 +5,15 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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import contact
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from tech import drc
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import debug
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import math
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from tech import layer
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from vector import vector
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from sram_factory import factory
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from globals import OPTS
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import logical_effort
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class single_level_column_mux_array(design.design):
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"""
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Dynamically generated column mux array.
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@ -26,13 +24,20 @@ class single_level_column_mux_array(design.design):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br))
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self.columns = columns
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self.word_size = word_size
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self.words_per_row = int(self.columns / self.word_size)
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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if "li" in layer:
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self.col_mux_stack = self.li_stack
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self.col_mux_stack_pitch = self.li_pitch
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else:
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self.col_mux_stack = self.m1_stack
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self.col_mux_stack_pitch = self.m1_pitch
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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@ -49,20 +54,20 @@ class single_level_column_mux_array(design.design):
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self.add_modules()
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self.add_pins()
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self.create_array()
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def create_layout(self):
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self.setup_layout_constants()
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self.place_array()
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self.add_routing()
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# Find the highest shapes to determine height before adding well
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highest = self.find_highest_coords()
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self.height = highest.y
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self.height = highest.y
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self.add_layout_pins()
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self.add_enclosure(self.mux_inst, "pwell")
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if "pwell" in layer:
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self.add_enclosure(self.mux_inst, "pwell")
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(self.columns):
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self.add_pin("bl_{}".format(i))
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@ -74,23 +79,19 @@ class single_level_column_mux_array(design.design):
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self.add_pin("br_out_{}".format(i))
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self.add_pin("gnd")
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def add_modules(self):
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self.mux = factory.create(module_type="single_level_column_mux",
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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self.add_mod(self.mux)
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def setup_layout_constants(self):
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self.column_addr_size = num_of_inputs = int(self.words_per_row / 2)
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self.column_addr_size = int(self.words_per_row / 2)
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self.width = self.columns * self.mux.width
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# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
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# one extra route pitch is to space from the sense amp
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self.route_height = (self.words_per_row + 3)*self.m1_pitch
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self.route_height = (self.words_per_row + 3) * self.col_mux_stack_pitch
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def create_array(self):
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self.mux_inst = []
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# For every column, add a pass gate
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@ -98,11 +99,11 @@ class single_level_column_mux_array(design.design):
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name = "XMUX{0}".format(col_num)
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self.mux_inst.append(self.add_inst(name=name,
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mod=self.mux))
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self.connect_inst(["bl_{}".format(col_num),
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"br_{}".format(col_num),
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"bl_out_{}".format(int(col_num/self.words_per_row)),
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"br_out_{}".format(int(col_num/self.words_per_row)),
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"bl_out_{}".format(int(col_num / self.words_per_row)),
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"br_out_{}".format(int(col_num / self.words_per_row)),
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"sel_{}".format(col_num % self.words_per_row),
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"gnd"])
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@ -117,32 +118,31 @@ class single_level_column_mux_array(design.design):
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else:
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mirror = ""
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name = "XMUX{0}".format(col_num)
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offset = vector(xoffset, self.route_height)
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self.mux_inst[col_num].place(offset=offset, mirror=mirror)
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def add_layout_pins(self):
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""" Add the pins after we determine the height. """
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# For every column, add a pass gate
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for col_num in range(self.columns):
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mux_inst = self.mux_inst[col_num]
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offset = mux_inst.get_pin("bl").ll()
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bl_pin = mux_inst.get_pin("bl")
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offset = bl_pin.ll()
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self.add_layout_pin(text="bl_{}".format(col_num),
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layer="m2",
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layer=bl_pin.layer,
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offset=offset,
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height=self.height-offset.y)
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height=self.height - offset.y)
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offset = mux_inst.get_pin("br").ll()
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br_pin = mux_inst.get_pin("br")
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offset = br_pin.ll()
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self.add_layout_pin(text="br_{}".format(col_num),
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layer="m2",
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layer=br_pin.layer,
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offset=offset,
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height=self.height-offset.y)
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height=self.height - offset.y)
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for inst in self.mux_inst:
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self.copy_layout_pin(inst, "gnd")
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def add_routing(self):
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self.add_horizontal_input_rail()
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self.add_vertical_poly_rail()
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@ -151,15 +151,15 @@ class single_level_column_mux_array(design.design):
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def add_horizontal_input_rail(self):
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""" Create address input rails on M1 below the mux transistors """
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for j in range(self.words_per_row):
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offset = vector(0, self.route_height + (j-self.words_per_row)*self.m1_pitch)
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offset = vector(0, self.route_height + (j - self.words_per_row) * self.col_mux_stack_pitch) #edit
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self.add_layout_pin(text="sel_{}".format(j),
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layer="m1",
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layer=self.col_mux_stack[0],
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offset=offset,
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width=self.mux.width * self.columns)
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def add_vertical_poly_rail(self):
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""" Connect the poly to the address rails """
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# Offset to the first transistor gate in the pass gate
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for col in range(self.columns):
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# which select bit should this column connect to depends on the position in the word
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@ -167,11 +167,12 @@ class single_level_column_mux_array(design.design):
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# Add the column x offset to find the right select bit
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gate_offset = self.mux_inst[col].get_pin("sel").bc()
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# height to connect the gate to the correct horizontal row
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sel_height = self.get_pin("sel_{}".format(sel_index)).by()
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# sel_height = self.get_pin("sel_{}".format(sel_index)).by()
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# use the y offset from the sel pin and the x offset from the gate
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offset = vector(gate_offset.x,self.get_pin("sel_{}".format(sel_index)).cy())
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offset = vector(gate_offset.x,
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self.get_pin("sel_{}".format(sel_index)).cy())
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# Add the poly contact with a shift to account for the rotation
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self.add_via_center(layers=("m1", "contact", "poly"),
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self.add_via_center(layers=self.poly_stack,
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offset=offset)
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self.add_path("poly", [offset, gate_offset])
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@ -182,11 +183,11 @@ class single_level_column_mux_array(design.design):
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bl_offset = self.mux_inst[j].get_pin("bl_out").bc()
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br_offset = self.mux_inst[j].get_pin("br_out").bc()
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bl_out_offset = bl_offset - vector(0,(self.words_per_row+1)*self.m1_pitch)
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br_out_offset = br_offset - vector(0,(self.words_per_row+2)*self.m1_pitch)
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bl_out_offset = bl_offset - vector(0, (self.words_per_row + 1) * self.col_mux_stack_pitch)
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br_out_offset = br_offset - vector(0, (self.words_per_row + 2) * self.col_mux_stack_pitch)
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bl_out_offset_end = bl_out_offset + vector(0,self.route_height)
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br_out_offset_end = br_out_offset + vector(0,self.route_height)
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bl_out_offset_end = bl_out_offset + vector(0, self.route_height)
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br_out_offset_end = br_out_offset + vector(0, self.route_height)
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if cell_properties.bitcell.mirror.y and j % 2:
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tmp_bl_out_end = br_out_offset_end
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@ -208,43 +209,41 @@ class single_level_column_mux_array(design.design):
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else:
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dist = 0
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self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width+dist,0)])
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self.add_path("m1", [br_out_offset, br_out_offset+vector(width-dist,0)])
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self.add_path(self.col_mux_stack[0], [bl_out_offset, bl_out_offset + vector(width + dist, 0)])
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self.add_path(self.col_mux_stack[0], [br_out_offset, br_out_offset + vector(width - dist, 0)])
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# Extend the bitline output rails and gnd downward on the first bit of each n-way mux
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self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j/self.words_per_row)),
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layer="m2",
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self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j / self.words_per_row)),
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layer=self.col_mux_stack[2],
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start=bl_out_offset,
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end=tmp_bl_out_end)
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self.add_layout_pin_segment_center(text="br_out_{}".format(int(j/self.words_per_row)),
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layer="m2",
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self.add_layout_pin_segment_center(text="br_out_{}".format(int(j / self.words_per_row)),
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layer=self.col_mux_stack[2],
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start=br_out_offset,
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end=tmp_br_out_end)
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# This via is on the right of the wire
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self.add_via_center(layers=self.m1_stack,
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# This via is on the right of the wire
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self.add_via_center(layers=self.col_mux_stack,
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offset=bl_out_offset)
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# This via is on the left of the wire
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=br_out_offset)
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else:
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self.add_path("m2", [ bl_out_offset, tmp_bl_out_end])
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self.add_path("m2", [ br_out_offset, tmp_br_out_end])
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self.add_path(self.col_mux_stack[2], [bl_out_offset, bl_offset])
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self.add_path(self.col_mux_stack[2], [br_out_offset, br_offset])
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# This via is on the right of the wire
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=bl_out_offset)
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# This via is on the left of the wire
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self.add_via_center(layers=self.m1_stack,
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# This via is on the left of the wire
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self.add_via_center(layers=self.col_mux_stack,
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offset=br_out_offset)
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the NMOS pass TX"""
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from tech import parameter
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#Bitcell drain load being used to estimate mux NMOS drain load
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# Bitcell drain load being used to estimate mux NMOS drain load
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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return drain_load
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return drain_load
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@ -121,13 +121,25 @@ class single_level_column_mux(pgate.pgate):
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# height is the distance between the nmos' diffusions, which depends on max(self.active_space,self.poly_space)
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offset = self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active)
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height = self.nmos_upper.get_pin("G").by() + self.poly_extend_active - offset.y
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self.add_layout_pin(text="sel",
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layer="poly",
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self.add_rect(layer="poly",
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offset=offset,
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height=height)
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# Add the sel pin to the bottom of the mux
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self.add_layout_pin(text="sel",
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layer="poly",
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offset=self.nmos_lower.get_pin("G").ll(),
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height=self.poly_extend_active)
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def connect_bitlines(self):
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""" Connect the bitlines to the mux transistors """
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# If li exists, use li and m1 for the mux, otherwise use m1 and m2
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if "li" in layer:
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self.col_mux_stack = self.li_stack
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else:
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self.col_mux_stack = self.m1_stack
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# These are on metal2
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bl_pin = self.get_pin("bl")
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br_pin = self.get_pin("br")
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@ -140,29 +152,24 @@ class single_level_column_mux(pgate.pgate):
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nmos_upper_s_pin = self.nmos_upper.get_pin("S")
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nmos_upper_d_pin = self.nmos_upper.get_pin("D")
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# If li exists, use li and m1 for the mux, otherwise use m1 and m2
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if "li" in layer:
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col_mux_stack = self.li_stack
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else:
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col_mux_stack = self.m1_stack
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# Add vias to bl, br_out, nmos_upper/S, nmos_lower/D
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self.add_via_center(layers=col_mux_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=bl_pin.bc(),
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directions=("V", "V"))
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self.add_via_center(layers=col_mux_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=br_out_pin.uc(),
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directions=("V", "V"))
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self.add_via_center(layers=col_mux_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=nmos_upper_s_pin.center(),
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directions=("V", "V"))
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self.add_via_center(layers=col_mux_stack,
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self.add_via_center(layers=self.col_mux_stack,
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offset=nmos_lower_d_pin.center(),
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directions=("V", "V"))
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# Add diffusion contacts
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# These were previously omitted with the options: add_source_contact=False, add_drain_contact=False
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# They are added now and not previously due to a s8 tech special case in which the contacts intersected the mux intraconnect
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# They are added now and not previously so that they do not include m1 (which is usually included by default)
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# This is only a concern when the local interconnect (li) layer is being used
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self.add_via_center(layers=self.active_stack,
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offset=nmos_upper_d_pin.center(),
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directions=("V", "V"),
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@ -186,7 +193,7 @@ class single_level_column_mux(pgate.pgate):
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# bl -> nmos_upper/D on metal1
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# bl_out -> nmos_upper/S on metal2
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self.add_path(col_mux_stack[0],
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self.add_path(self.col_mux_stack[0],
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[bl_pin.ll(), vector(nmos_upper_d_pin.cx(), bl_pin.by()),
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nmos_upper_d_pin.center()])
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# halfway up, move over
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@ -194,12 +201,12 @@ class single_level_column_mux(pgate.pgate):
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+ nmos_upper_s_pin.bc().scale(0, 0.4)
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mid2 = bl_out_pin.uc().scale(0, 0.4) \
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+ nmos_upper_s_pin.bc().scale(1, 0.4)
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self.add_path(col_mux_stack[2],
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self.add_path(self.col_mux_stack[2],
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[bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.center()])
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# br -> nmos_lower/D on metal2
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# br_out -> nmos_lower/S on metal1
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self.add_path(col_mux_stack[0],
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self.add_path(self.col_mux_stack[0],
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[br_out_pin.uc(),
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vector(nmos_lower_s_pin.cx(), br_out_pin.uy()),
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nmos_lower_s_pin.center()])
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@ -208,7 +215,7 @@ class single_level_column_mux(pgate.pgate):
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+ nmos_lower_d_pin.uc().scale(0,0.5)
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mid2 = br_pin.bc().scale(0,0.5) \
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+ nmos_lower_d_pin.uc().scale(1,0.5)
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self.add_path(col_mux_stack[2],
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self.add_path(self.col_mux_stack[2],
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[br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()])
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def add_wells(self):
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@ -225,6 +232,10 @@ class single_level_column_mux(pgate.pgate):
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implant_type="p",
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well_type="p")
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# If there is a li layer, include it in the power stack
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self.add_via_center(layers=self.col_mux_stack,
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offset=active_pos)
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# Add the M1->..->power_grid_layer stack
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self.add_power_pin(name = "gnd",
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loc = active_pos,
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