single port progess

.vscode/launch.json

@@ -0,0 +1,59 @@
+{
+    // Use IntelliSense to learn about possible attributes.
+    // Hover to view descriptions of existing attributes.
+    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
+    "version": "0.2.0",
+    "configurations": [
+
+
+
+        {
+            "name": "s8",
+            "type": "python",
+            "request": "launch",
+            "program": "/home/jesse/openram/compiler/openram.py",
+            "console": "integratedTerminal",
+            "args": ["-s", "ngspice", "-d", "-c", "-v", "-v", "/home/jesse/compiler/example_configs/s8config.py"]
+        },
+        {
+            "name": "pinv_10x",
+            "type": "python",
+            "request": "launch",
+            "program": "/home/jesse/openram/compiler/tests/04_pinv_10x_test.py",
+            "console": "integratedTerminal",
+            "args": ["-s", "ngspice", "-d", "-v", "-v", "-t", "s8"]
+        },
+        {
+            "name": "pinv_1x",
+            "type": "python",
+            "request": "launch",
+            "program": "/home/jesse/openram/compiler/tests/04_pinv_1x_test.py",
+            "console": "integratedTerminal",
+            "args": ["-s", "ngspice", "-d", "-v", "-v", "-t", "s8"]
+        },
+        {
+            "name": "scmos-pex",
+            "type": "python",
+            "request": "launch",
+            "program": "/home/jesse/openram/compiler/openram.py",
+            "console": "integratedTerminal",
+            "args": ["-s", "ngspice", "-d", "-v", "-b", "/home/jesse/compiler/example_configs/run2.py"]
+        },
+        {
+            "name": "router",
+            "type": "python",
+            "request": "launch",
+            "program": "/home/jesse/openram/compiler/openram.py",
+            "console": "integratedTerminal",
+            "args": ["-s", "ngspice", "-d", "-v", "-v", "/home/jesse/compiler/example_configs/example_config_scn4m_subm.py"]
+        },
+        {
+            "name": "decoder",
+            "type": "python",
+            "request": "launch",
+            "program": "/home/jesse/openram/compiler/tests/05_bitcell_array_test.py",
+            "console": "integratedTerminal",
+            "args": ["-s", "ngspice", "-d", "-t", "sky130", "-v"]
+        }
+    ]
+} 

b3v32check.log

@@ -0,0 +1,4 @@
+BSIM3 Model (Supports: v3.2, v3.2.2, v3.2.3, v3.2.4)
+Parameter Checking.
+Model = npd.0
+W = 2.1e-07, L = 1.5e-07, M = 1

compiler/.vscode/launch.json

@@ -0,0 +1,15 @@
+{
+    // Use IntelliSense to learn about possible attributes.
+    // Hover to view descriptions of existing attributes.
+    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "name": "Python: Current File",
+            "type": "python",
+            "request": "launch",
+            "program": "${file}",
+            "console": "integratedTerminal"
+        }
+    ]
+}

compiler/b3v32check.log

@@ -0,0 +1,4 @@
+BSIM3 Model (Supports: v3.2, v3.2.2, v3.2.3, v3.2.4)
+Parameter Checking.
+Model = npd.0
+W = 2.1e-07, L = 1.5e-07, M = 1

compiler/b3v3_1check.log

@@ -0,0 +1,5 @@
+BSIM3V3.1 Parameter Check
+Model = p
+W = 6e-07, L = 8e-07
+Warning: Pd = 0 is less than W.
+Warning: Ps = 0 is less than W.

compiler/base/custom_cell_properties.py

@@ -31,15 +31,22 @@ class _mirror_axis:
         self.y = y
 
 class _bitcell:
-    def __init__(self, mirror, split_wl, cell_6t, cell_1rw1r, cell_1w1r):
+    def __init__(self, mirror, split_wl, cell_s8_6t, cell_6t, cell_1rw1r, cell_1w1r):
         self.mirror = mirror
         self.split_wl = split_wl
+        self._s8_6t = cell_s8_6t
         self._6t = cell_6t
         self._1rw1r = cell_1rw1r
         self._1w1r = cell_1w1r
 
     def _default():
         axis = _mirror_axis(True, False)
+
+        cell_s8_6t = _cell({'bl' : 'bl0',
+                            'br' : 'bl1',
+                            'wl0': 'wl0',
+                            'wl1': 'wl1'})
+
         cell_6t = _cell({'bl' : 'bl',
                          'br' : 'br',
                          'wl' : 'wl'})
@@ -50,18 +57,25 @@ class _bitcell:
                        'br1' : 'br1',
                        'wl0' : 'wl0',
                        'wl1' : 'wl1'})
+
         cell_1w1r =  _cell({'bl0' : 'bl0',
                        'br0' : 'br0',
                        'bl1' : 'bl1',
                        'br1' : 'br1',
                        'wl0' : 'wl0',
                        'wl1' : 'wl1'})
-        return _bitcell(cell_6t=cell_6t,
+
+        return _bitcell(cell_s8_6t=cell_s8_6t,
+                        cell_6t=cell_6t,
                         cell_1rw1r=cell_1rw1r,
                         cell_1w1r=cell_1w1r,
                         split_wl = False,
                         mirror=axis)
 
+    @property
+    def cell_s8_6t(self):
+        return self._s8_6t
+
     @property
     def cell_6t(self):
         return self._6t

compiler/base/utils.py

@@ -73,7 +73,7 @@ def auto_measure_libcell(pin_list, name, units, lpp):
     return cell
 
 
-def get_gds_size(name, gds_filename, units, lpp):
+def get_gds_size(name, gds_filename, units, lpp, structure = ""):
     """
     Open a GDS file and return the size from either the
     bounding box or a border layer.
@@ -83,7 +83,7 @@ def get_gds_size(name, gds_filename, units, lpp):
     reader = gdsMill.Gds2reader(cell_vlsi)
     reader.loadFromFile(gds_filename)
 
-    measure_result = cell_vlsi.getLayoutBorder(lpp)
+    measure_result = cell_vlsi.getLayoutBorder(lpp, structure)
     if not measure_result:
         debug.info(2, "Layout border failed. Trying to measure size for {}".format(name))
         measure_result = cell_vlsi.measureSize(name)
@@ -91,14 +91,14 @@ def get_gds_size(name, gds_filename, units, lpp):
     return measure_result
 
 
-def get_libcell_size(name, units, lpp):
+def get_libcell_size(name, units, lpp, structure = ""):
     """
     Open a GDS file and return the library cell size from either the
     bounding box or a border layer.
     """
 
     cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
-    return(get_gds_size(name, cell_gds, units, lpp))
+    return(get_gds_size(name, cell_gds, units, lpp, structure))
 
 
 

compiler/big.log

@@ -0,0 +1,57 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/giant_config_scn4m_subm.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/temp/
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell
+|==============================================================================|
+|=========                       OpenRAM v1.1.4                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 04/09/2020 05:13:06
+Technology: scn4m_subm
+Total size: 65536 bits
+Word size: 64
+Words: 1024
+Banks: 1
+Write size: None
+RW ports: 1
+R-only ports: 0
+W-only ports: 0
+Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[sram_config/recompute_sizes]: Recomputing with words per row: 4
+[sram_config/recompute_sizes]: Rows: 256 Cols: 256
+[sram_config/recompute_sizes]: Row addr size: 8 Col addr size: 2 Bank addr size: 10
+Words per row: 4
+Output files are: 
+/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.sp
+/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.v
+/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.lib
+/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.py
+/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.html
+/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.log
+/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.lef
+/home/jesse/openram/compiler/temp/sram_64_1024_scn4m_subm.gds
+[dff_array/__init__]: Creating row_addr_dff rows=8 cols=1
+[dff_array/__init__]: Creating col_addr_dff rows=1 cols=2
+[dff_array/__init__]: Creating data_dff rows=1 cols=64
+[precharge_array/__init__]: Creating precharge_array_0
+[sense_amp_array/__init__]: Creating sense_amp_array_0
+[single_level_column_mux_array/__init__]: Creating single_level_column_mux_array_0
+[write_driver_array/__init__]: Creating write_driver_array_0

compiler/bitcells/replica_bitcell.py

@@ -13,7 +13,7 @@ from tech import cell_properties as props
 
 from globals import OPTS
 
-class replica_bitcell(design.design):
+class s8_replica_bitcell(design.design):
     """
     A single bit cell (6T, 8T, etc.)
     This module implements the single memory cell used in the design. It

compiler/custom/s8_bitcell.py

@@ -0,0 +1,112 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import debug
+import utils
+from tech import GDS, layer
+from tech import cell_properties as props
+import bitcell_base
+from globals import OPTS
+
+class s8_bitcell(bitcell_base.bitcell_base):
+    """
+    A single bit cell (6T, 8T, etc.)  This module implements the
+    single memory cell used in the design. It is a hand-made cell, so
+    the layout and netlist should be available in the technology
+    library.
+    """
+
+    # If we have a split WL bitcell, if not be backwards
+    # compatible in the tech file
+
+    if props.bitcell.split_wl:
+        pin_names = ["bl0", "bl1", "wl0", "wl1", "vpwr", "vgnd"]
+        type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
+    else:
+        pin_names = [props.bitcell.cell_6t.pin.bl,
+                     props.bitcell.cell_6t.pin.br,
+                     props.bitcell.cell_6t.pin.wl,
+                     props.bitcell.cell_6t.pin.vdd,
+                     props.bitcell.cell_6t.pin.gnd]
+        type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
+    storage_nets = ['Q', 'Q_bar']
+
+    def __init__(self, version, name=""):
+        # Ignore the name argument
+
+
+        if version == "opt1":
+            self.name = "s8sram_cell_opt1"
+            self.border_structure = "s8sram_cell"
+        elif version == "opt1a":
+            self.name = "s8sram_cell_opt1a"
+            self.border_structure = "s8sram_cell"
+            
+        bitcell_base.bitcell_base.__init__(self, self.name)
+        debug.info(2, "Create bitcell")
+
+        self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
+
+
+
+        self.add_pin_types(self.type_list)
+        self.nets_match = self.do_nets_exist(self.storage_nets)       
+        
+        (self.width, self.height) = utils.get_libcell_size(self.name,
+                                        GDS["unit"],
+                                        layer["mem"],
+                                        "s8sram_cell\x00")
+
+
+        #debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells")
+              
+    def get_all_wl_names(self):
+        """ Creates a list of all wordline pin names """
+        if props.bitcell.split_wl:
+            row_pins = ["wl0", "wl1"]
+        else:
+            row_pins = [props.bitcell.s8_sp.pin.wl]
+        return row_pins
+
+    def get_all_bitline_names(self):
+        """ Creates a list of all bitline pin names (both bl and br) """
+        pin = props.bitcell.cell_s8_6t.pin
+        column_pins = [pin.bl, pin.br]
+        return column_pins
+
+    def get_all_bl_names(self):
+        """ Creates a list of all bl pins names """
+        return [props.bitcell.cell_s8_6t.pin.bl]
+
+    def get_all_br_names(self):
+        """ Creates a list of all br pins names """
+        return [props.bitcell.cell_s8_6t.pin.br]
+
+    def get_bl_name(self, port=0):
+        """Get bl name"""
+        debug.check(port == 0, "One port for bitcell only.")
+        return props.bitcell.cell_s8_6t.pin.bl
+
+    def get_br_name(self, port=0):
+        """Get bl name"""
+        debug.check(port == 0, "One port for bitcell only.")
+        return props.bitcell.cell_s8_6t.pin.br
+
+    def get_wl_name(self, port=0):
+        """Get wl name"""
+        if props.bitcell.split_wl:
+            return "wl{}".format(port)
+        else:
+            debug.check(port == 0, "One port for bitcell only.")
+            return props.bitcell.cell_s8_6t.pin.wl
+
+    def build_graph(self, graph, inst_name, port_nets):
+        """
+        Adds edges based on inputs/outputs.
+        Overrides base class function.
+        """
+        self.add_graph_edges(graph, port_nets)

compiler/custom/s8_col_end.py

@@ -0,0 +1,40 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+import debug
+import design
+import utils
+from globals import OPTS
+from tech import parameter, drc, layer, GDS
+
+class s8_col_end(design.design):
+
+
+    def __init__(self, version, name=""):
+        super().__init__(name)
+        pin_names = []
+        type_list = []
+
+        if version == "colend":
+            self.name = "s8sram16x16_colend"
+        elif version == "colend_p_cent":
+            self.name = "s8sram16x16_colend_p_cent"
+        elif version == "colenda":
+            self.name = "s8sram16x16_colenda"
+        elif version == "colenda_p_cent":
+            self.name = "s8sram16x16_colenda_p_cent"
+        else:
+            debug.error("Invalid type for col_end", -1)
+        design.design.__init__(self, name=self.name)
+        (self.width, self.height) = utils.get_libcell_size(self.name,
+                                        GDS["unit"],
+                                        layer["mem"])
+        pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
+
+
+    

compiler/custom/s8_corner.py

@@ -0,0 +1,37 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+import debug
+import design
+import utils
+from globals import OPTS
+from tech import parameter, drc, layer, GDS
+
+class s8_corner(design.design):
+
+
+    def __init__(self, location, name=""):
+        super().__init__(name)
+        pin_names = []
+        type_list = []
+        
+        if location == "ul":
+            self.name = "s8sram16x16_corner"
+        elif location == "ur":
+            self.name = "s8sram16x16_cornerb"
+        elif location == "ll":
+            self.name = "s8sram16x16_cornera"
+        elif location == "lr":
+            self.name = "s8sram16x16_cornerb"
+        else:
+            debug.error("Invalid s8_corner location", -1)
+        design.design.__init__(self, name=self.name)
+        (self.width, self.height) = utils.get_libcell_size(self.name,
+                                        GDS["unit"],
+                                        layer["mem"])
+        pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])

compiler/custom/s8_internal.py

@@ -0,0 +1,36 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+import debug
+import design
+import utils
+from globals import OPTS
+from tech import parameter, drc, layer, GDS
+
+class s8_internal(design.design):
+
+
+    def __init__(self, version, name=""):
+        super().__init__(name)
+        pin_names = []
+        type_list = []
+        
+        if version == "wlstrap":
+            self.name = "s8sram_wlstrap"
+            self.structure = "s8sram_wlstrap_ce\x00"
+        elif version == "wlstrap_p":
+            self.name = "s8sram16x16_wlstrap_p"
+            self.structure = "s8sram16x16_wlstrap_p_ce"
+        else:
+            debug.error("Invalid version", -1)
+        design.design.__init__(self, name=self.name)
+        (self.width, self.height) = utils.get_libcell_size(self.name,
+                                        GDS["unit"],
+                                        layer["mem"],
+                                        self.structure)
+        pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])

compiler/custom/s8_replica_bitcell.py

@@ -0,0 +1,76 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import design
+import debug
+import utils
+from tech import GDS,layer,drc,parameter,cell_properties
+from tech import cell_properties as props
+
+from globals import OPTS
+
+class replica_bitcell(design.design):
+    """
+    A single bit cell (6T, 8T, etc.)
+    This module implements the single memory cell used in the design. It
+    is a hand-made cell, so the layout and netlist should be available in
+    the technology library. """
+
+    if cell_properties.bitcell.split_wl:
+        pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
+        type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] 
+    else:
+        pin_names = [props.bitcell.cell_6t.pin.bl,
+                     props.bitcell.cell_6t.pin.br,
+                     props.bitcell.cell_6t.pin.wl,
+                     props.bitcell.cell_6t.pin.vdd,
+                     props.bitcell.cell_6t.pin.gnd]
+
+        type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] 
+    
+    if not OPTS.netlist_only:
+        (width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"])
+        pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"])
+    else:
+        (width,height) = (0,0)
+        pin_map = []
+
+    def __init__(self, name=""):
+        # Ignore the name argument
+        design.design.__init__(self, "replica_cell_6t")
+        debug.info(2, "Create replica bitcell object")
+
+        self.width = replica_bitcell.width
+        self.height = replica_bitcell.height
+        self.pin_map = replica_bitcell.pin_map
+        self.add_pin_types(self.type_list)
+        
+    def get_stage_effort(self, load):
+        parasitic_delay = 1
+        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
+        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
+        read_port_load = 0.5 #min size NMOS gate load
+        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
+        
+    def input_load(self):
+        """Return the relative capacitance of the access transistor gates"""
+        
+        # FIXME: This applies to bitline capacitances as well.
+        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
+        return 2*access_tx_cin    
+    
+    def analytical_power(self, corner, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        dynamic = 0 #temporary
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
+
+    def build_graph(self, graph, inst_name, port_nets):        
+        """Adds edges based on inputs/outputs. Overrides base class function."""
+        self.add_graph_edges(graph, port_nets)

compiler/example_configs/run1.py

@@ -0,0 +1,19 @@
+word_size = 2
+num_words = 16
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+#netlist_only = True
+route_supplies = True
+check_lvsdrc = True
+
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/run2.py

@@ -0,0 +1,19 @@
+word_size = 8
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/run3.py

@@ -0,0 +1,18 @@
+word_size = 16
+num_words = 256
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/run4.py

@@ -0,0 +1,18 @@
+word_size = 32
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/run5.py

@@ -0,0 +1,19 @@
+word_size = 64
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+
+output_path = "/home/jesse/thesis/outputs/run5"
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/s8config.py

@@ -0,0 +1,31 @@
+word_size = 16
+num_words = 16
+
+num_rw_ports = 1
+num_r_ports = 0
+num_w_ports = 0
+
+tech_name = "sky130"
+
+
+
+accuracy_requirement = 0.05
+magic_exe = ("magic", "magic")
+nominal_corners_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+netlist_only = False
+route_supplies = "grid"
+check_lvsdrc = False
+
+#replica_bitcell_array = "/home/jesse/openram/technology/sky130/modules/replica_bitcell_array.py"
+
+output_path = "sram_" + str(accuracy_requirement)
+output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,
+                                        num_words,
+                                        tech_name,
+                                        accuracy_requirement
+                                        )
+write_size=8

compiler/gdsMill/gdsMill/vlsiLayout.py

@@ -593,9 +593,11 @@ class VlsiLayout:
                 passFailIndex += 1
         print("Done\n\n")
 
-    def getLayoutBorder(self, lpp):
+    def getLayoutBorder(self, lpp, structure = ""):
+        if structure == "":
+            structure = self.rootStructureName
         cellSizeMicron = None
-        for boundary in self.structures[self.rootStructureName].boundaries:
+        for boundary in self.structures[structure].boundaries:
             if sameLPP((boundary.drawingLayer, boundary.purposeLayer),
                        lpp):
                 if self.debug:
@@ -607,7 +609,7 @@ class VlsiLayout:
                 cellSizeMicron = [cellSize[0]*self.units[0],
                                   cellSize[1]*self.units[0]]
         debug.check(cellSizeMicron,
-                    "Error: "+str(self.rootStructureName)+".cell_size information not found yet")
+                    "Error: "+str(structure)+".cell_size information not found yet")
 
         return cellSizeMicron
 

compiler/modules/bitcell_array.py

@@ -6,6 +6,7 @@
 # All rights reserved.
 #
 from bitcell_base_array import bitcell_base_array
+from s8_corner import s8_corner
 from tech import drc, spice
 from globals import OPTS
 from sram_factory import factory
@@ -45,8 +46,29 @@ class bitcell_array(bitcell_base_array):
 
     def add_modules(self):
         """ Add the modules used in this design """
-        self.cell = factory.create(module_type="bitcell")
-        self.add_mod(self.cell)
+        if OPTS.tech_name != "sky130":
+            self.cell = factory.create(module_type="bitcell")
+            self.add_mod(self.cell)
+
+        else:
+            #self.add_mod(factory.create(module_type="s8_corner", location = "ul"))
+            #self.add_mod(factory.create(module_type="s8_corner", location = "ur"))
+            #self.add_mod(factory.create(module_type="s8_corner", location = "ll"))
+            #self.add_mod(factory.create(module_type="s8_corner", location = "lr"))
+
+            #self.add_mod(factory.create(module_type="s8_col_end", version = "colenda"))
+            #self.add_mod(factory.create(module_type="s8_col_end", version = "colenda"))
+            #self.add_mod(factory.create(module_type="s8_col_end", version = "colend_p_cent"))
+            #self.add_mod(factory.create(module_type="s8_col_end", version = "colenda_p_cent"))
+            
+            self.add_mod(factory.create(module_type="s8_bitcell", version = "opt1"))
+            self.add_mod(factory.create(module_type="s8_bitcell", version = "opt1a"))
+
+            self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
+            self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
+            
+
+
 
     def create_instances(self):
         """ Create the module instances used in this design """

compiler/modules/bitcell_base_array.py

@@ -9,6 +9,7 @@ import debug
 import design
 from tech import cell_properties
 from sram_factory import factory
+from globals import OPTS
 
 
 class bitcell_base_array(design.design):
@@ -25,8 +26,14 @@ class bitcell_base_array(design.design):
         self.column_offset = column_offset
 
         # Bitcell for port names only
-        self.cell = factory.create(module_type="bitcell")
-        
+        if OPTS.tech_name != "sky130":
+            self.cell = factory.create(module_type="bitcell")
+        else:
+            self.cell = factory.create(module_type="s8_bitcell", version="opt1")
+            self.cell2 = factory.create(module_type="s8_bitcell", version="opt1a")
+            self.strap = factory.create(module_type="s8_internal", version="wlstrap")
+            self.strap2 = factory.create(module_type="s8_internal", version="wlstrap_p")
+
         self.create_all_bitline_names()
         self.create_all_wordline_names()
 
@@ -49,7 +56,11 @@ class bitcell_base_array(design.design):
         self.wordline_names = [[] for port in self.all_ports]
         for row in range(self.row_size):
             for port in self.all_ports:
-                self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
+                if not cell_properties.bitcell.split_wl:
+                    self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
+                else:
+                    self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
+                    self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
         self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
         
     def get_bitline_names(self, port=None):
@@ -65,13 +76,20 @@ class bitcell_base_array(design.design):
             return self.wordline_names[port]
         
     def add_pins(self):
-        for bl_name in self.get_bitline_names():
-            self.add_pin(bl_name, "INOUT")
-        for wl_name in self.get_wordline_names():
-            self.add_pin(wl_name, "INPUT")
-        self.add_pin("vdd", "POWER")
-        self.add_pin("gnd", "GROUND")
-
+        if OPTS.tech_name != "sky130":
+            for bl_name in self.get_bitline_names():
+                self.add_pin(bl_name, "INOUT")
+            for wl_name in self.get_wordline_names():
+                self.add_pin(wl_name, "INPUT")
+            self.add_pin("vdd", "POWER")
+            self.add_pin("gnd", "GROUND")
+        else:
+            for bl_name in self.get_bitline_names():
+                self.add_pin(bl_name, "INOUT")
+            for wl_name in self.get_wordline_names():
+                self.add_pin(wl_name, "INPUT")
+            self.add_pin("vpwr", "POWER")
+            self.add_pin("vgnd", "GROUND")
     def get_bitcell_pins(self, row, col):
         """ Creates a list of connections in the bitcell,
         indexed by column and row, for instance use in bitcell_array """
@@ -86,40 +104,78 @@ class bitcell_base_array(design.design):
 
     def add_layout_pins(self):
         """ Add the layout pins """
-
-        bitline_names = self.cell.get_all_bitline_names()
-        for col in range(self.column_size):
-            for port in self.all_ports:
-                bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
-                self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
-                                    layer=bl_pin.layer,
-                                    offset=bl_pin.ll().scale(1, 0),
-                                    width=bl_pin.width(),
-                                    height=self.height)
-                br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
-                self.add_layout_pin(text="br_{0}_{1}".format(port, col),
-                                    layer=br_pin.layer,
-                                    offset=br_pin.ll().scale(1, 0),
-                                    width=br_pin.width(),
-                                    height=self.height)
-
-        wl_names = self.cell.get_all_wl_names()
-        for row in range(self.row_size):
-            for port in self.all_ports:
-                wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
-                self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
-                                    layer=wl_pin.layer,
-                                    offset=wl_pin.ll().scale(0, 1),
-                                    width=self.width,
-                                    height=wl_pin.height())
-
-        # Copy a vdd/gnd layout pin from every cell
-        for row in range(self.row_size):
+        if OPTS.tech_name != "sky130":
+            bitline_names = self.cell.get_all_bitline_names()
             for col in range(self.column_size):
-                inst = self.cell_inst[row, col]
-                for pin_name in ["vdd", "gnd"]:
-                    self.copy_layout_pin(inst, pin_name)
+                for port in self.all_ports:
+                    bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
+                    self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
+                                        layer=bl_pin.layer,
+                                        offset=bl_pin.ll().scale(1, 0),
+                                        width=bl_pin.width(),
+                                        height=self.height)
+                    br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
+                    self.add_layout_pin(text="br_{0}_{1}".format(port, col),
+                                        layer=br_pin.layer,
+                                        offset=br_pin.ll().scale(1, 0),
+                                        width=br_pin.width(),
+                                        height=self.height)
 
+            wl_names = self.cell.get_all_wl_names()
+            for row in range(self.row_size):
+                for port in self.all_ports:
+                    wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
+                    self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
+                                        layer=wl_pin.layer,
+                                        offset=wl_pin.ll().scale(0, 1),
+                                        width=self.width,
+                                        height=wl_pin.height())
+
+            # Copy a vdd/gnd layout pin from every cell
+            for row in range(self.row_size):
+                for col in range(self.column_size):
+                    inst = self.cell_inst[row, col]
+                    for pin_name in ["vdd", "gnd"]:
+                        self.copy_layout_pin(inst, pin_name)
+        else:
+            bitline_names = self.cell.get_all_bitline_names()
+            for col in range(self.column_size):
+                for port in self.all_ports:
+                    bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
+                    self.add_layout_pin(text="bl0_{0}_{1}".format(port, col),
+                                        layer=bl_pin.layer,
+                                        offset=bl_pin.ll().scale(1, 0),
+                                        width=bl_pin.width(),
+                                        height=self.height)
+                    br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
+                    self.add_layout_pin(text="bl1_{0}_{1}".format(port, col),
+                                        layer=br_pin.layer,
+                                        offset=br_pin.ll().scale(1, 0),
+                                        width=br_pin.width(),
+                                        height=self.height)
+
+            wl_names = self.cell.get_all_wl_names()
+            for row in range(self.row_size):
+                for port in self.all_ports:
+                    wl0_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
+                    self.add_layout_pin(text="wl0_{0}_{1}".format(port, row),
+                                        layer=wl0_pin.layer,
+                                        offset=wl0_pin.ll().scale(0, 1),
+                                        width=self.width,
+                                        height=wl0_pin.height())
+                    wl1_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
+                    self.add_layout_pin(text="wl1_{0}_{1}".format(port, row),
+                                        layer=wl1_pin.layer,
+                                        offset=wl1_pin.ll().scale(0, 1),
+                                        width=self.width,
+                                        height=wl1_pin.height())
+            # Copy a vdd/gnd layout pin from every cell
+            for row in range(self.row_size):
+                for col in range(self.column_size):
+                    inst = self.cell_inst[row, col]
+                    for pin_name in ["vpwr", "vgnd"]:
+
+                        self.copy_layout_pin(inst, pin_name)
     def _adjust_x_offset(self, xoffset, col, col_offset):
         tempx = xoffset
         dir_y = False
@@ -140,27 +196,66 @@ class bitcell_base_array(design.design):
 
     def place_array(self, name_template, row_offset=0):
         # We increase it by a well enclosure so the precharges don't overlap our wells
-        self.height = self.row_size * self.cell.height
-        self.width = self.column_size * self.cell.width
+        if OPTS.tech_name != "sky130":
+            self.height = self.row_size * self.cell.height
+            self.width = self.column_size * self.cell.width
+
+            xoffset = 0.0
+            for col in range(self.column_size):
+                yoffset = 0.0
+                tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
+
+                for row in range(self.row_size):
+                    tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
+
+                    if dir_x and dir_y:
+                        dir_key = "XY"
+                    elif dir_x:
+                        dir_key = "MX"
+                    elif dir_y:
+                        dir_key = "MY"
+                    else:
+                        dir_key = ""
+
+                    self.cell_inst[row, col].place(offset=[tempx, tempy],
+                                                mirror=dir_key)
+                    yoffset += self.cell.height
+                xoffset += self.cell.width
+        else:
+            array_layout = []
+            for y in range(0,self.row_size):
+
+                row_layout = []
+                alternate_bitcell = 1
+                alternate_strap = 1
+                for x in range(0,self.column_size):
+                    if alternate_bitcell == 1:
+                        row_layout.append(self.cell)
+                        alternate_bitcell = 0
+                    else:
+                        row_layout.append(self.cell2)
+                        alternate_bitcell = 1
+                    if x != self.column_size:
+                        if alternate_strap:
+                            row_layout.append(self.strap2)
+                            alternate_strap = 0
+                        else:
+                            
+                            row_layout.append(self.strap)
+                            alternate_strap = 1
+                array_layout.append(row_layout)
+
+            self.height = self.row_size * self.cell.height + (self.row_size - 1) * self.strap.height
+            self.width = self.column_size * self.cell.width + (self.column_size-1) * self.strap.width
+            
 
-        xoffset = 0.0
-        for col in range(self.column_size):
             yoffset = 0.0
-            tempx, dir_y = self._adjust_x_offset(xoffset, col, self.column_offset)
 
-            for row in range(self.row_size):
-                tempy, dir_x = self._adjust_y_offset(yoffset, row, row_offset)
-
-                if dir_x and dir_y:
-                    dir_key = "XY"
-                elif dir_x:
-                    dir_key = "MX"
-                elif dir_y:
-                    dir_key = "MY"
-                else:
-                    dir_key = ""
-
-                self.cell_inst[row, col].place(offset=[tempx, tempy],
-                                               mirror=dir_key)
+            for row in range(0, len(array_layout)):
+                xoffset = 0.0               
+                for col in range(0, len(array_layout[row])):
+                    inst = self.add_inst(name = "row_{}, col_{}".format(row,col), mod=array_layout[row][col])
+                    inst.place(offset=[xoffset, yoffset])
+                    xoffset += inst.width
                 yoffset += self.cell.height
-            xoffset += self.cell.width
+                

compiler/modules/custom_cell.py

@@ -0,0 +1,271 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import design
+import debug
+from tech import drc
+from sram_factory import factory
+from vector import vector
+from globals import OPTS
+
+
+class custom_cell(design.design):
+    """
+    Array of tristate drivers to write to the bitlines through the column mux.
+    Dynamically generated write driver array of all bitlines.
+    """
+
+    def __init__(self, name, pins, mod):
+
+        design.design.__init__(self, name)
+        debug.info(1, "Creating {0}".format(self.name))
+        self.add_comment("columns: {0}".format(columns))
+        self.add_comment("word_size {0}".format(word_size))
+
+        self.columns = columns
+        self.word_size = word_size
+        self.write_size = write_size
+        self.column_offset = column_offset
+        self.words_per_row = int(columns / word_size)
+        if not num_spare_cols:
+            self.num_spare_cols = 0
+        else:
+            self.num_spare_cols = num_spare_cols
+
+        if self.write_size:
+            self.num_wmasks = int(self.word_size / self.write_size)
+
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+    def get_bl_name(self):
+        bl_name = "bl"
+        return bl_name
+
+    def get_br_name(self):
+        br_name = "br"
+        return br_name
+
+    @property
+    def data_name(self):
+        return "data"
+
+    @property
+    def en_name(self):
+        return "en"
+
+    def create_netlist(self):
+        self.add_modules()
+        self.add_pins()
+        self.create_write_array()
+
+    def create_layout(self):
+
+        if self.bitcell.width > self.driver.width:
+            self.width = (self.columns + self.num_spare_cols) * self.bitcell.width
+            self.width_regular_cols = self.columns * self.bitcell.width
+            self.single_col_width = self.bitcell.width
+        else:
+            self.width = (self.columns + self.num_spare_cols) * self.driver.width
+            self.width_regular_cols = self.columns * self.driver.width
+            self.single_col_width = self.driver.width
+        self.height = self.driver.height
+
+        self.place_write_array()
+        self.add_layout_pins()
+        self.add_boundary()
+        self.DRC_LVS()
+
+    def add_pins(self):
+        for i in range(self.word_size + self.num_spare_cols):
+            self.add_pin(self.data_name + "_{0}".format(i), "INPUT")
+        for i in range(self.word_size + self.num_spare_cols):
+            self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT")
+            self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT")
+        if self.write_size:
+            for i in range(self.num_wmasks + self.num_spare_cols):
+                self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
+        elif self.num_spare_cols and not self.write_size:
+            for i in range(self.num_spare_cols + 1):
+                self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
+        else:
+            self.add_pin(self.en_name, "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
+
+    def add_modules(self):
+        self.driver = factory.create(module_type="write_driver")
+        self.add_mod(self.driver)
+
+        # This is just used for measurements,
+        # so don't add the module
+        self.bitcell = factory.create(module_type="bitcell")
+
+    def create_write_array(self):
+        self.driver_insts = {}
+        w = 0
+        windex=0
+        for i in range(0, self.columns, self.words_per_row):
+            name = "write_driver{}".format(i)
+            index = int(i / self.words_per_row)
+            self.driver_insts[index]=self.add_inst(name=name,
+                                                   mod=self.driver)
+
+            if self.write_size:
+                self.connect_inst([self.data_name + "_{0}".format(index),
+                                   self.get_bl_name() + "_{0}".format(index),
+                                   self.get_br_name() + "_{0}".format(index),
+                                   self.en_name + "_{0}".format(windex), "vdd", "gnd"])
+                w+=1
+                # when w equals write size, the next en pin can be connected since we are now at the next wmask bit
+                if w == self.write_size:
+                    w = 0
+                    windex+=1
+            
+            elif self.num_spare_cols and not self.write_size:
+                self.connect_inst([self.data_name + "_{0}".format(index),
+                                   self.get_bl_name() + "_{0}".format(index),
+                                   self.get_br_name() + "_{0}".format(index),
+                                   self.en_name + "_{0}".format(0), "vdd", "gnd"])
+            
+            else:
+                self.connect_inst([self.data_name + "_{0}".format(index),
+                                   self.get_bl_name() + "_{0}".format(index),
+                                   self.get_br_name() + "_{0}".format(index),
+                                   self.en_name, "vdd", "gnd"])
+
+        for i in range(self.num_spare_cols):
+            index = self.word_size + i
+            if self.write_size:
+                offset = self.num_wmasks
+            else:
+                offset = 1
+            name = "write_driver{}".format(self.columns + i)
+            self.driver_insts[index]=self.add_inst(name=name,
+                                                   mod=self.driver)
+
+            self.connect_inst([self.data_name + "_{0}".format(index),
+                               self.get_bl_name() + "_{0}".format(index),
+                               self.get_br_name() + "_{0}".format(index),
+                               self.en_name + "_{0}".format(i + offset), "vdd", "gnd"])
+
+    def place_write_array(self):
+        from tech import cell_properties
+        if self.bitcell.width > self.driver.width:
+            self.driver_spacing = self.bitcell.width
+        else:
+            self.driver_spacing = self.driver.width
+        for i in range(0, self.columns, self.words_per_row):
+            index = int(i / self.words_per_row)
+            xoffset = i * self.driver_spacing
+
+            if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
+                mirror = "MY"
+                xoffset = xoffset + self.driver.width
+            else:
+                mirror = ""
+
+            base = vector(xoffset, 0)
+            self.driver_insts[index].place(offset=base, mirror=mirror)
+
+        # place spare write drivers (if spare columns are specified)
+        for i in range(self.num_spare_cols):
+            index = self.word_size + i
+            xoffset = (self.columns + i) * self.driver_spacing
+                
+            if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
+                mirror = "MY"
+                xoffset = xoffset + self.driver.width
+            else:
+                mirror = ""
+              
+            base = vector(xoffset, 0)
+            self.driver_insts[index].place(offset=base, mirror=mirror)
+
+    def add_layout_pins(self):
+        for i in range(self.word_size + self.num_spare_cols):
+            inst = self.driver_insts[i]
+            din_pin = inst.get_pin(inst.mod.din_name)
+            self.add_layout_pin(text=self.data_name + "_{0}".format(i),
+                                layer=din_pin.layer,
+                                offset=din_pin.ll(),
+                                width=din_pin.width(),
+                                height=din_pin.height())
+            bl_pin = inst.get_pin(inst.mod.get_bl_names())
+            self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
+                                layer=bl_pin.layer,
+                                offset=bl_pin.ll(),
+                                width=bl_pin.width(),
+                                height=bl_pin.height())
+
+            br_pin = inst.get_pin(inst.mod.get_br_names())
+            self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
+                                layer=br_pin.layer,
+                                offset=br_pin.ll(),
+                                width=br_pin.width(),
+                                height=br_pin.height())
+
+            for n in ["vdd", "gnd"]:
+                pin_list = self.driver_insts[i].get_pins(n)
+                for pin in pin_list:
+                    self.add_power_pin(name=n,
+                                       loc=pin.center(),
+                                       directions=("V", "V"),
+                                       start_layer=pin.layer)
+        if self.write_size:
+            for bit in range(self.num_wmasks):
+                inst = self.driver_insts[bit * self.write_size]
+                en_pin = inst.get_pin(inst.mod.en_name)
+                # Determine width of wmask modified en_pin with/without col mux
+                wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
+                if (self.words_per_row == 1):
+                    en_gap = self.driver_spacing - en_pin.width()
+                else:
+                    en_gap = self.driver_spacing
+
+                self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
+                                    layer=en_pin.layer,
+                                    offset=en_pin.ll(),
+                                    width=wmask_en_len - en_gap,
+                                    height=en_pin.height())
+            
+            for i in range(self.num_spare_cols):
+                inst = self.driver_insts[self.word_size + i]
+                en_pin = inst.get_pin(inst.mod.en_name)
+                self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks),
+                                    layer="m1",
+                                    offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
+         
+        elif self.num_spare_cols and not self.write_size:
+            # shorten enable rail to accomodate those for spare write drivers
+            inst = self.driver_insts[0]
+            en_pin = inst.get_pin(inst.mod.en_name)
+            self.add_layout_pin(text=self.en_name + "_{0}".format(0),
+                                layer="m1",
+                                offset=en_pin.ll(),
+                                width=self.width_regular_cols - self.words_per_row * en_pin.width())
+
+            # individual enables for every spare write driver
+            for i in range(self.num_spare_cols):
+                inst = self.driver_insts[self.word_size + i]
+                en_pin = inst.get_pin(inst.mod.en_name)
+                self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1),
+                                    layer="m1",
+                                    offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
+
+        else:
+            inst = self.driver_insts[0]
+            self.add_layout_pin(text=self.en_name,
+                                layer="m1",
+                                offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1),
+                                width=self.width)
+
+    def get_w_en_cin(self):
+        """Get the relative capacitance of all the enable connections in the bank"""
+        # The enable is connected to a nand2 for every row.
+        return self.driver.get_w_en_cin() * len(self.driver_insts)

compiler/modules/orig_bitcell_array.py

@@ -0,0 +1,117 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+from bitcell_base_array import bitcell_base_array
+from tech import drc, spice
+from globals import OPTS
+from sram_factory import factory
+
+
+class bitcell_array(bitcell_base_array):
+    """
+    Creates a rows x cols array of memory cells. Assumes bit-lines
+    and word line is connected by abutment.
+    Connects the word lines and bit lines.
+    """
+    def __init__(self, cols, rows, name, column_offset=0):
+        super().__init__(cols, rows, name, column_offset)
+
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+
+        # We don't offset this because we need to align
+        # the replica bitcell in the control logic
+        # self.offset_all_coordinates()
+        
+    def create_netlist(self):
+        """ Create and connect the netlist """
+        self.add_modules()
+        self.add_pins()
+        self.create_instances()
+
+    def create_layout(self):
+
+        self.place_array("bit_r{0}_c{1}")
+
+        self.add_layout_pins()
+
+        self.add_boundary()
+        
+        self.DRC_LVS()
+
+    def add_modules(self):
+        """ Add the modules used in this design """
+        self.cell = factory.create(module_type="bitcell")
+        self.add_mod(self.cell)
+
+    def create_instances(self):
+        """ Create the module instances used in this design """
+        self.cell_inst = {}
+        for col in range(self.column_size):
+            for row in range(self.row_size):
+                name = "bit_r{0}_c{1}".format(row, col)
+                self.cell_inst[row, col]=self.add_inst(name=name,
+                                                       mod=self.cell)
+                self.connect_inst(self.get_bitcell_pins(col, row))
+        
+    def analytical_power(self, corner, load):
+        """Power of Bitcell array and bitline in nW."""
+        
+        # Dynamic Power from Bitline
+        bl_wire = self.gen_bl_wire()
+        cell_load = 2 * bl_wire.return_input_cap()
+        bl_swing = OPTS.rbl_delay_percentage
+        freq = spice["default_event_frequency"]
+        bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
+        
+        # Calculate the bitcell power which currently only includes leakage
+        cell_power = self.cell.analytical_power(corner, load)
+        
+        # Leakage power grows with entire array and bitlines.
+        total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
+                                        cell_power.leakage * self.column_size * self.row_size)
+        return total_power
+
+    def gen_wl_wire(self):
+        if OPTS.netlist_only:
+            width = 0
+        else:
+            width = self.width
+        wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_m1"))
+        wl_wire.wire_c = 2 * spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
+        return wl_wire
+
+    def gen_bl_wire(self):
+        if OPTS.netlist_only:
+            height = 0
+        else:
+            height = self.height
+        bl_pos = 0
+        bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
+        bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
+        return bl_wire
+
+    def get_wordline_cin(self):
+        """Get the relative input capacitance from the wordline connections in all the bitcell"""
+        # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
+        bitcell_wl_cin = self.cell.get_wl_cin()
+        total_cin = bitcell_wl_cin * self.column_size
+        return total_cin
+        
+    def graph_exclude_bits(self, targ_row, targ_col):
+        """Excludes bits in column from being added to graph except target"""
+        # Function is not robust with column mux configurations
+        for row in range(self.row_size):
+            for col in range(self.column_size):
+                if row == targ_row and col == targ_col:
+                    continue
+                self.graph_inst_exclude.add(self.cell_inst[row, col])
+            
+    def get_cell_name(self, inst_name, row, col):
+        """Gets the spice name of the target bitcell."""
+        return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col]

compiler/modules/replica_bitcell_array.py

@@ -88,7 +88,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
         ^ dummy columns  ^
           1 x (rows + 4)
         """
-
         # Bitcell array
         self.bitcell_array = factory.create(module_type="bitcell_array",
                                             column_offset=1 + self.add_left_rbl,
@@ -109,6 +108,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
                 replica_bit = self.left_rbl + self.row_size + 1 + bit
             # If we have an odd numer on the bottom
             column_offset = self.left_rbl + 1
+
             self.replica_columns[bit] = factory.create(module_type="replica_column",
                                                        rows=self.row_size,
                                                        rbl=self.rbl,

compiler/riscv/sram_1rw1r_32_256_8_s8.log

@@ -0,0 +1,7 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/skywater-tech/riscv_1k_s8.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/riscv/
+[globals/import_tech]: Importing technology: s8
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology

compiler/riscv/sram_1rw1r_32_256_8_sky130.log

@@ -0,0 +1,61 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/skywater-tech/riscv_1k_s8.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/riscv/
+[globals/import_tech]: Importing technology: sky130
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/25/2020 07:53:43
+Technology: sky130
+Total size: 8192 bits
+Word size: 32
+Words: 256
+Banks: 1
+Write size: 8
+RW ports: 1
+R-only ports: 1
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
+[sram_config/recompute_sizes]: Recomputing with words per row: 2
+[sram_config/recompute_sizes]: Rows: 128 Cols: 64
+[sram_config/recompute_sizes]: Row addr size: 7 Col addr size: 1 Bank addr size: 8
+Words per row: 2
+Output files are: 
+/home/jesse/openram/compiler/riscv/sram_1rw1r_32_256_8_sky130.sp
+/home/jesse/openram/compiler/riscv/sram_1rw1r_32_256_8_sky130.v
+/home/jesse/openram/compiler/riscv/sram_1rw1r_32_256_8_sky130.lib
+/home/jesse/openram/compiler/riscv/sram_1rw1r_32_256_8_sky130.py
+/home/jesse/openram/compiler/riscv/sram_1rw1r_32_256_8_sky130.html
+/home/jesse/openram/compiler/riscv/sram_1rw1r_32_256_8_sky130.log
+/home/jesse/openram/compiler/riscv/sram_1rw1r_32_256_8_sky130.lef
+/home/jesse/openram/compiler/riscv/sram_1rw1r_32_256_8_sky130.gds
+[sram/__init__]: create sram of size 32 with 256 num of words 1 banks
+[dff_array/__init__]: Creating row_addr_dff rows=7 cols=1
+[dff_array/__init__]: Creating col_addr_dff rows=1 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=32
+[dff_array/__init__]: Creating wmask_dff rows=1 cols=4
+[bank/__init__]: create sram of size 32 with 256 words
+[port_data/__init__]: create data port of size 32 with 2 words per row
+[precharge/__init__]: creating precharge cell precharge
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55

compiler/run.sh

@@ -0,0 +1 @@
+python openram.py ../technology/s8/s8.py -v -v -d -c 

compiler/scmos_run/sram_2_16_s8.log

@@ -0,0 +1,76 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/temp/
+[globals/import_tech]: Importing technology: s8
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: Finding DRC/LVS/PEX tools.
+[globals/get_tool]: Finding DRC tool...
+[globals/get_tool]: Using DRC: /usr/local/bin/magic
+[globals/get_tool]: Finding LVS tool...
+[globals/get_tool]: Using LVS: /usr/local/bin/netgen
+[globals/get_tool]: Finding PEX tool...
+[globals/get_tool]: Using PEX: /usr/local/bin/magic
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Finding spice simulator.
+[globals/get_tool]: Finding spice tool...
+[globals/get_tool]: Could not find hspice, trying next spice tool.
+[globals/get_tool]: Using spice: /usr/local/bin/ngspice
+[globals/setup_bitcell]: Using bitcell: bitcell
+|==============================================================================|
+|=========                       OpenRAM v1.1.4                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 04/18/2020 04:50:34
+Technology: s8
+Total size: 32 bits
+Word size: 2
+Words: 16
+Banks: 1
+Write size: None
+RW ports: 1
+R-only ports: 0
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+Performing simulation-based characterization with ngspice
+[bitcell/__init__]: Create bitcell
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 2
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/temp/sram_2_16_s8.sp
+/home/jesse/openram/compiler/temp/sram_2_16_s8.v
+/home/jesse/openram/compiler/temp/sram_2_16_s8.lib
+/home/jesse/openram/compiler/temp/sram_2_16_s8.py
+/home/jesse/openram/compiler/temp/sram_2_16_s8.html
+/home/jesse/openram/compiler/temp/sram_2_16_s8.log
+/home/jesse/openram/compiler/temp/sram_2_16_s8.lef
+/home/jesse/openram/compiler/temp/sram_2_16_s8.gds
+[sram/__init__]: create sram of size 2 with 16 num of words 1 banks
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=2
+[bank/__init__]: create sram of size 2 with 16 words
+[port_data/__init__]: create data port of size 2 with 1 words per row
+[precharge/__init__]: creating precharge cell precharge_0
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
+[precharge_array/__init__]: Creating precharge_array_0
+[precharge/__init__]: creating precharge cell precharge_1
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
+[sense_amp_array/__init__]: Creating sense_amp_array_0
+[sense_amp/__init__]: Create sense_amp
+[write_driver_array/__init__]: Creating write_driver_array_0
+[write_driver/__init__]: Create write_driver
+ERROR: file hierarchy_layout.py: line 1092: Cyclic VCG in channel router.
+

compiler/scmos_run/sram_2_16_scn4m_subm.log

@@ -0,0 +1,241 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/example_config_scn4m_subm.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/temp/
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: Finding DRC/LVS/PEX tools.
+[globals/get_tool]: Using DRC: /usr/local/bin/magic
+[globals/get_tool]: Using LVS: /usr/local/bin/netgen
+[globals/get_tool]: Using PEX: /usr/local/bin/magic
+[globals/setup_bitcell]: Using bitcell: bitcell
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Finding spice simulator.
+[globals/get_tool]: Could not find hspice, trying next spice tool.
+[globals/get_tool]: Using spice: /usr/local/bin/ngspice
+|==============================================================================|
+|=========                       OpenRAM v1.1.2                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 04/23/2020 00:06:42
+Technology: scn4m_subm
+Total size: 32 bits
+Word size: 2
+Words: 16
+Banks: 1
+Write size: None
+RW ports: 1
+R-only ports: 0
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+Performing simulation-based characterization with ngspice
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 2
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.sp
+/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.v
+/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.lib
+/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.py
+/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.html
+/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.log
+/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.lef
+/home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.gds
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=2
+[precharge_array/__init__]: Creating precharge_array_0
+[sense_amp_array/__init__]: Creating sense_amp_array_0
+[write_driver_array/__init__]: Creating write_driver_array_0
+[wordline_driver/__init__]: Creating wordline_driver_0
+[pdriver/__init__]: creating pdriver pdriver_0
+[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 16 x 2
+[bitcell_array/__init__]: Creating bitcell_array_0 16 x 2
+[dummy_array/__init__]: Creating dummy_array_0 1 x 2
+[dummy_array/__init__]: Creating dummy_array_1 19 x 1
+[control_logic/__init__]: Creating control_logic_rw
+[dff_buf/__init__]: Creating dff_buf
+[dff_buf_array/__init__]: Creating dff_buf_array_0
+[dff_buf/__init__]: Creating dff_buf_0
+[pand2/__init__]: Creating pnand2 pand2_0
+[pdriver/__init__]: creating pdriver pdriver_1
+[pbuf/__init__]: creating pbuf_0 with size of 2
+[pdriver/__init__]: creating pdriver pdriver_2
+[pdriver/__init__]: creating pdriver pdriver_3
+[pand3/__init__]: Creating pand3 pand3_0
+[pand3/__init__]: Creating pand3 pand3_1
+[pdriver/__init__]: creating pdriver pdriver_4
+[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
+** Submodules: 0.4 seconds
+** Placement: 0.0 seconds
+[router_tech/__init__]: Track width: 2.400
+[router_tech/__init__]: Track space: 1.200
+[router_tech/__init__]: Track wire width: 1.200
+[supply_grid_router/route]: Running supply router on vdd and gnd...
+[supply_grid_router/create_routing_grid]: Size: 227.0 x 371.80000000000007
+**** Retrieving pins: 0.0 seconds
+**** Analyzing pins: 0.7 seconds
+[router/find_blockages]: Finding blockages.
+**** Finding blockages: 0.1 seconds
+[router/convert_blockages]: Converting blockages.
+**** Converting blockages: 0.0 seconds
+[router/convert_pins]: Converting pins for vdd.
+[router/convert_pins]: Converting pins for gnd.
+**** Converting pins: 0.5 seconds
+[router/separate_adjacent_pin]: Comparing vdd and gnd adjacency
+[router/separate_adjacent_pin]: Removed 0 adjacent grids.
+**** Separating adjacent pins: 0.1 seconds
+[router/enclose_pins]: Enclosing pins for vdd
+[router/enclose_pins]: Enclosing pins for gnd
+**** Enclosing pins: 0.2 seconds
+*** Finding pins and blockages: 1.4 seconds
+[supply_grid_router/route_supply_rails]: Routing supply rail gnd.
+[supply_grid_router/route_supply_rails]: Routing supply rail vdd.
+*** Routing supply rails: 1.1 seconds
+[supply_grid_router/route_simple_overlaps]: Routing simple overlap pins for vdd
+[supply_grid_router/route_simple_overlaps]: Routed 96 simple overlap pins
+[supply_grid_router/route_simple_overlaps]: Routing simple overlap pins for gnd
+[supply_grid_router/route_simple_overlaps]: Routed 172 simple overlap pins
+*** Simple overlap routing: 0.0 seconds
+[supply_grid_router/route_pins_to_rails]: Maze routing vdd with 11 pin components to connect.
+[router/run_router]: Found path: cost=2 
+[router/run_router]: [[v3d[7, 72, 0]], [v3d[7, 72, 1]]]
+[router/run_router]: Found path: cost=2 
+[router/run_router]: [[v3d[7, 54, 0]], [v3d[7, 54, 1]]]
+[router/run_router]: Found path: cost=4 
+[router/run_router]: [[v3d[14, 63, 0]], [v3d[14, 64, 0]]]
+[router/run_router]: Found path: cost=4 
+[router/run_router]: [[v3d[14, 55, 0]], [v3d[14, 56, 0]]]
+[router/run_router]: Found path: cost=1 
+[router/run_router]: [[v3d[14, 80, 0]], [v3d[13, 80, 0]]]
+[router/run_router]: Found path: cost=4 
+[router/run_router]: [[v3d[14, 71, 0]], [v3d[14, 70, 0]]]
+[router/run_router]: Found path: cost=2 
+[router/run_router]: [[v3d[41, 123, 0]], [v3d[41, 123, 1]]]
+[router/run_router]: Found path: cost=2 
+[router/run_router]: [[v3d[45, 123, 0]], [v3d[45, 123, 1]]]
+[router/run_router]: Found path: cost=2 
+[router/run_router]: [[v3d[47, 123, 0]], [v3d[47, 123, 1]]]
+[router/run_router]: Found path: cost=2 
+[router/run_router]: [[v3d[51, 123, 0]], [v3d[51, 123, 1]]]
+[router/run_router]: Found path: cost=2 
+[router/run_router]: [[v3d[53, 123, 0]], [v3d[53, 123, 1]]]
+[supply_grid_router/route_pins_to_rails]: Maze routing gnd with 5 pin components to connect.
+[router/run_router]: Found path: cost=4 
+[router/run_router]: [[v3d[-6, 124, 0]], [v3d[-6, 123, 0]]]
+[router/run_router]: Found path: cost=4 
+[router/run_router]: [[v3d[6, 58, 0]], [v3d[6, 57, 0]]]
+[router/run_router]: Found path: cost=4 
+[router/run_router]: [[v3d[14, 68, 0]], [v3d[14, 69, 0]]]
+[router/run_router]: Found path: cost=4 
+[router/run_router]: [[v3d[14, 58, 0]], [v3d[14, 57, 0]]]
+[router/run_router]: Found path: cost=1 
+[router/run_router]: [[v3d[14, 85, 0]], [v3d[13, 85, 0]]]
+*** Maze routing supplies: 2.9 seconds
+** Routing: 7.6 seconds
+[verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm	0
+[verify.magic/run_lvs]: sram_2_16_scn4m_subm	LVS matches
+** Verification: 6.6 seconds
+** SRAM creation: 14.7 seconds
+LEF: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.lef
+** LEF: 0.6 seconds
+GDS: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.gds
+** GDS: 0.2 seconds
+SP: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.sp
+** Spice writing: 0.0 seconds
+** Extraction: 5.6 seconds
+LIB: Characterizing... 
+[characterizer.lib/prepare_tables]: Loads: [ 2.45605  9.8242  78.5936 ]
+[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05   0.4   ]
+[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
+[characterizer.delay/find_feasible_period_one_port]: Trying feasible period: 10.0ns on Port 0
+[characterizer.delay/find_feasible_period]: Found feasible_period: 10.0ns
+[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 5.0ns (ub: 10.0 lb: 0.0)
+[characterizer.delay/check_bit_measures]: Wrong value detected on probe bit during read/write cycle. Check writes and control logic for bugs.
+ measure=v_qbar_a1111_b1_WRITE_ZERO, op=WRITE_ZERO, bit_storage=INVERTING, V(bit)=0.6127083
+[characterizer.delay/check_read_debug_measures]: Debug measurement failed. Value 4.987059V was read on read 0 cycle.
+[characterizer.delay/check_bitline_meas]: min_dicharge=False, min_diff=False
+[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 7.5ns (ub: 10.0 lb: 5.0)
+[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 8.75ns (ub: 10.0 lb: 7.5)
+[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 9.375ns (ub: 10.0 lb: 8.75)
+[characterizer.delay/find_min_period_one_port]: MinPeriod Search Port 0: 9.0625ns (ub: 9.375 lb: 8.75)
+[characterizer.delay/analyze]: Min Period Found: 9.0625ns
+[characterizer.delay/run_power_simulation]: Performing leakage power simulations.
+[characterizer.delay/run_power_simulation]: Leakage power of full array is 0.4069451 mW
+[characterizer.delay/run_power_simulation]: Leakage power of trimmed array is 0.4069451 mW
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.0125 load=2.45605
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.0125 load=9.8242
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.0125 load=78.5936
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.05 load=2.45605
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.05 load=9.8242
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.05 load=78.5936
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.4 load=2.45605
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.4 load=9.8242
+[characterizer.delay/simulate_loads_and_slews]: Simulation Passed: Port All slew=0.4 load=78.5936
+[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.2001953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.1757812
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.11718749999999999
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.09277344
+[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.1879883
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.1757812
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.11718749999999999
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.09277344
+[characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.2368164
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.24902339999999998
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.2148437
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.08056640999999999
+[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.2001953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.1757812
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.11718749999999999
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.09277344
+[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.1879883
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.1757812
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.11718749999999999
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.09277344
+[characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.2368164
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.24902339999999998
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.2148437
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.08056640999999999
+[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.2001953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.1757812
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.11718749999999999
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.09277344
+[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.1879883
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.1757812
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.11718749999999999
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.09277344
+[characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.2368164
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.24902339999999998
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.2148437
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.08056640999999999
+** Characterization: 1028.4 seconds
+Config: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.py
+** Config: 0.0 seconds
+Datasheet: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.html
+** Datasheet: 0.0 seconds
+Verilog: Writing to /home/jesse/openram/compiler/temp/sram_2_16_scn4m_subm.v
+** Verilog: 0.0 seconds
+[globals/cleanup_paths]: Preserving temp directory: /home/jesse/output/
+[verify.magic/print_drc_stats]: DRC runs: 1
+[verify.magic/print_lvs_stats]: LVS runs: 1
+[verify.magic/print_pex_stats]: PEX runs: 1
+** End: 1049.5 seconds

compiler/scmos_run/sram_2_16_scn4m_subm.py

@@ -0,0 +1,19 @@
+word_size = 2
+num_words = 16
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+
+output_path = "temp"
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/scmos_run/sram_2_16_scn4m_subm.v

@@ -0,0 +1,61 @@
+// OpenRAM SRAM model
+// Words: 16
+// Word size: 2
+
+module sram_2_16_scn4m_subm(
+// Port 0: RW
+    clk0,csb0,web0,addr0,din0,dout0
+  );
+
+  parameter DATA_WIDTH = 2 ;
+  parameter ADDR_WIDTH = 4 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    dout0 = 2'bx;
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg )
+        mem[addr0_reg] = din0_reg;
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+endmodule

compiler/scmos_run/sram_2_16_scn4m_subm_TT_5p0V_25C.lib

@@ -0,0 +1,321 @@
+library (sram_2_16_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0785936");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_2_16_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 2;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 85520.32;
+
+    leakage_power () {
+      when : "csb0";
+      value : 0.4069451;
+    }
+    cell_leakage_power : 0;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.2, 0.188, 0.237",\
+                   "0.2, 0.188, 0.237",\
+                   "0.2, 0.188, 0.237");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.176, 0.176, 0.249",\
+                   "0.176, 0.176, 0.249",\
+                   "0.176, 0.176, 0.249");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.117, -0.117, -0.215",\
+                   "-0.117, -0.117, -0.215",\
+                   "-0.117, -0.117, -0.215");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.093, -0.093, -0.081",\
+                   "-0.093, -0.093, -0.081",\
+                   "-0.093, -0.093, -0.081");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0785936;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[1:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("2.389, 2.429, 2.787",\
+                   "2.393, 2.433, 2.79",\
+                   "2.452, 2.492, 2.849");
+            }
+            cell_fall(CELL_TABLE) {
+            values("2.389, 2.429, 2.787",\
+                   "2.393, 2.433, 2.79",\
+                   "2.452, 2.492, 2.849");
+            }
+            rise_transition(CELL_TABLE) {
+            values("2.516, 2.525, 2.635",\
+                   "2.516, 2.525, 2.635",\
+                   "2.516, 2.525, 2.635");
+            }
+            fall_transition(CELL_TABLE) {
+            values("2.516, 2.525, 2.635",\
+                   "2.516, 2.525, 2.635",\
+                   "2.516, 2.525, 2.635");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.2, 0.188, 0.237",\
+                   "0.2, 0.188, 0.237",\
+                   "0.2, 0.188, 0.237");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.176, 0.176, 0.249",\
+                   "0.176, 0.176, 0.249",\
+                   "0.176, 0.176, 0.249");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.117, -0.117, -0.215",\
+                   "-0.117, -0.117, -0.215",\
+                   "-0.117, -0.117, -0.215");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.093, -0.093, -0.081",\
+                   "-0.093, -0.093, -0.081",\
+                   "-0.093, -0.093, -0.081");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.2, 0.188, 0.237",\
+                   "0.2, 0.188, 0.237",\
+                   "0.2, 0.188, 0.237");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.176, 0.176, 0.249",\
+                   "0.176, 0.176, 0.249",\
+                   "0.176, 0.176, 0.249");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.117, -0.117, -0.215",\
+                   "-0.117, -0.117, -0.215",\
+                   "-0.117, -0.117, -0.215");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.093, -0.093, -0.081",\
+                   "-0.093, -0.093, -0.081",\
+                   "-0.093, -0.093, -0.081");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.2, 0.188, 0.237",\
+                   "0.2, 0.188, 0.237",\
+                   "0.2, 0.188, 0.237");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.176, 0.176, 0.249",\
+                   "0.176, 0.176, 0.249",\
+                   "0.176, 0.176, 0.249");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.117, -0.117, -0.215",\
+                   "-0.117, -0.117, -0.215",\
+                   "-0.117, -0.117, -0.215");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.093, -0.093, -0.081",\
+                   "-0.093, -0.093, -0.081",\
+                   "-0.093, -0.093, -0.081");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & clk0 & !web0"; 
+            rise_power(scalar){
+                values("6.961670277777778");
+            }
+            fall_power(scalar){
+                values("6.961670277777778");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & !clk0 & web0"; 
+            rise_power(scalar){
+                values("6.824691944444444");
+            }
+            fall_power(scalar){
+                values("6.824691944444444");
+            }
+        }
+        internal_power(){
+            when : "csb0"; 
+            rise_power(scalar){
+                values("0");
+            }
+            fall_power(scalar){
+                values("0");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("4.531"); 
+            }
+            fall_constraint(scalar) {
+                values("4.531"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("9.062"); 
+            }
+            fall_constraint(scalar) {
+                values("9.062"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_0.01/sram_16_16_sky130_0.01.log

@@ -0,0 +1,295 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/sram_0.01/
+[globals/import_tech]: Importing technology: sky130
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/25/2020 17:07:05
+Technology: sky130
+Total size: 256 bits
+Word size: 16
+Words: 16
+Banks: 1
+Write size: 8
+RW ports: 1
+R-only ports: 1
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 16
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/sram_0.01/sram_16_16_sky130_0.01.sp
+/home/jesse/openram/compiler/sram_0.01/sram_16_16_sky130_0.01.v
+/home/jesse/openram/compiler/sram_0.01/sram_16_16_sky130_0.01.lib
+/home/jesse/openram/compiler/sram_0.01/sram_16_16_sky130_0.01.py
+/home/jesse/openram/compiler/sram_0.01/sram_16_16_sky130_0.01.html
+/home/jesse/openram/compiler/sram_0.01/sram_16_16_sky130_0.01.log
+/home/jesse/openram/compiler/sram_0.01/sram_16_16_sky130_0.01.lef
+/home/jesse/openram/compiler/sram_0.01/sram_16_16_sky130_0.01.gds
+[sram/__init__]: create sram of size 16 with 16 num of words 1 banks
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=16
+[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
+[bank/__init__]: create sram of size 16 with 16 words
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge/__init__]: creating precharge cell precharge
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning pmos tx, target: 1.26, found 3.0 x 1 = 3.0
+[precharge_array/__init__]: Creating precharge_array
+[precharge/__init__]: creating precharge cell precharge_0
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[sense_amp_array/__init__]: Creating sense_amp_array
+[sense_amp/__init__]: Create sense_amp
+[write_driver_array/__init__]: Creating write_driver_array
+[write_driver/__init__]: Create write_driver
+[write_mask_and_array/__init__]: Creating write_mask_and_array
+[pand2/__init__]: Creating pand2 pand2
+[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 3.0 x 1 = 3.0
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 3.0, found 7.0 x 1 = 7.0
+[pdriver/__init__]: creating pdriver pdriver
+[pinv/__init__]: creating pinv structure pinv with size of 2.0
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 1.0 x 1 = 1.0
+[pgate/bin_width]: binning pmos tx, target: 0.36, found 1.0 x 1 = 1.0
+[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 2 pinv bin error: 0.06481481481481488 percent error 0.03240740740740744
+[pgate/bin_width]: binning nmos tx, target: 0.74, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 1.12, found 3.0 x 1 = 3.0
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge_array/__init__]: Creating precharge_array_0
+[precharge/__init__]: creating precharge cell precharge_1
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[port_address/__init__]: create data port of cols 16 rows 16
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1
+[pinv/__init__]: creating pinv structure pinv_dec with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 1.0 x 1 = 1.0
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 3.0 x 1 = 3.0
+[pgate/bin_width]: binning nmos tx, target: 1.0, found 3.0 x 1 = 3.0
+[pgate/bin_width]: binning pmos tx, target: 3.0, found 7.0 x 1 = 7.0
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 16
+[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 16
+[pgate/bin_width]: binning nmos tx, target: 5.76, found 7.0 x 1 = 7.0
+[pgate/bin_width]: binning pmos tx, target: 17.28, found 7.0 x 3 = 21.0
+[pgate/bin_width]: binning nmos tx, target: 7.0, found 7.0 x 1 = 7.0
+[pgate/bin_width]: binning pmos tx, target: 7.0, found 7.0 x 1 = 7.0
+[replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 16
+[bitcell_base_array/__init__]: Creating bitcell_array 16 x 16
+[replica_bitcell_1rw_1r/__init__]: Create replica bitcell 1rw+1r object
+[dummy_bitcell_1rw_1r/__init__]: Create dummy bitcell 1rw+1r object
+[col_cap_bitcell_1rw_1r/__init__]: Create col_cap bitcell 1rw+1r object
+[bitcell_base_array/__init__]: Creating dummy_array 1 x 16
+[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16
+[bitcell_base_array/__init__]: Creating row_cap_array 20 x 1
+[row_cap_bitcell_1rw_1r/__init__]: Create row_cap bitcell 1rw+1r object
+[bitcell_base_array/__init__]: Creating row_cap_array_0 20 x 1
+[control_logic/__init__]: Creating control_logic_rw
+[dff_buf/__init__]: Creating dff_buf
+[pinv/__init__]: creating pinv structure pinv_0 with size of 2
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 4 pinv bin error: 0.12962962962962976 percent error 0.03240740740740744
+[pinv/__init__]: creating pinv structure pinv_1 with size of 4
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
+[pinv/determine_tx_mults]: pinv bin count: 6 pinv bin error: 0.44212962962962954 percent error 0.07368827160493825
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 1.6499999999999997, found 3.0 x 1 = 3.0
+[dff_buf_array/__init__]: Creating dff_buf_array
+[dff_buf/__init__]: Creating dff_buf_0
+[pand2/__init__]: Creating pand2 pand2_0
+[pnand2/__init__]: creating pnand2 structure pnand2_0 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 3.0 x 1 = 3.0
+[pdriver/__init__]: creating pdriver pdriver_0
+[pinv/__init__]: creating pinv structure pinv_2 with size of 12
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 8 pinv bin error: 0.6890432098765432 percent error 0.0861304012345679
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pbuf/__init__]: creating pbuf with size of 16
+[pinv/__init__]: creating pinv structure pinv_3 with size of 16
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: pinv bin count: 10 pinv bin error: 0.7723765432098766 percent error 0.07723765432098766
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pdriver/__init__]: creating pdriver pdriver_1
+[pinv/__init__]: creating pinv structure pinv_4 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 12 pinv bin error: 0.8094135802469137 percent error 0.0674511316872428
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 1.0 x 1 = 1.0
+[pgate/bin_width]: binning pmos tx, target: 1.12, found 3.0 x 1 = 3.0
+[pinv/__init__]: creating pinv structure pinv_5 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 14 pinv bin error: 0.8464506172839508 percent error 0.06046075837742505
+[pinv/__init__]: creating pinv structure pinv_6 with size of 4
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
+[pinv/determine_tx_mults]: pinv bin count: 16 pinv bin error: 1.1589506172839505 percent error 0.07243441358024691
+[pinv/__init__]: creating pinv structure pinv_7 with size of 13
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 14.04, found 2.0 x 8 = 16.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.68, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 18 pinv bin error: 1.3754748338081673 percent error 0.07641526854489818
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pinv/__init__]: creating pinv structure pinv_8 with size of 38
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 41.04, found 2.0 x 21 = 42.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.68, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: pinv bin count: 20 pinv bin error: 1.4222584595391614 percent error 0.07111292297695807
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pdriver/__init__]: creating pdriver pdriver_2
+[pinv/__init__]: creating pinv structure pinv_9 with size of 2
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 22 pinv bin error: 1.4870732743539763 percent error 0.06759423974336255
+[pinv/__init__]: creating pinv structure pinv_10 with size of 5
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 5.3999999999999995, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.7999999999999998, found 2.0 x 1 = 2.0
+[pinv/determine_tx_mults]: pinv bin count: 24 pinv bin error: 1.7092954965761986 percent error 0.07122064569067495
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pand3/__init__]: Creating pand3 pand3
+[pnand3/__init__]: creating pnand3 structure pnand3 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 3.0 x 1 = 3.0
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pdriver/__init__]: creating pdriver pdriver_3
+[pinv/__init__]: creating pinv structure pinv_11 with size of 24
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 25.919999999999998, found 2.0 x 13 = 26.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 8.64, found 2.0 x 5 = 10.0
+[pinv/determine_tx_mults]: pinv bin count: 26 pinv bin error: 1.8697893237366925 percent error 0.07191497398987279
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pand3/__init__]: Creating pand3 pand3_0
+[pdriver/__init__]: creating pdriver pdriver_4
+[pinv/__init__]: creating pinv structure pinv_12 with size of 16
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: pinv bin count: 28 pinv bin error: 1.9531226570700257 percent error 0.06975438060964377
+[pinv/__init__]: creating pinv structure pinv_13 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 30 pinv bin error: 1.9901596941070627 percent error 0.06633865647023543
+[pnand2/__init__]: creating pnand2 structure pnand2_1 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 3.0 x 1 = 3.0
+[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
+[pinv/__init__]: creating pinv structure pinv_14 with size of 1
+[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 32 pinv bin error: 2.0271967311441 percent error 0.06334989784825312
+[control_logic/__init__]: Creating control_logic_r
+[dff_buf_array/__init__]: Creating dff_buf_array_0
+[pdriver/__init__]: creating pdriver pdriver_5
+[pinv/__init__]: creating pinv structure pinv_15 with size of 12
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 34 pinv bin error: 2.2741103113910133 percent error 0.06688559739385333
+[pinv/__init__]: creating pinv structure pinv_16 with size of 37
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 39.96, found 2.0 x 20 = 40.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.32, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: pinv bin count: 36 pinv bin error: 2.3261623634430655 percent error 0.06461562120675182
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 5.0 x 1 = 5.0
+** Submodules: 1.3 seconds
+** Placement: 0.0 seconds
+[router_tech/__init__]: Track width: 0.680
+[router_tech/__init__]: Track space: 0.300
+[router_tech/__init__]: Track wire width: 0.380
+[router_tech/__init__]: Track factor: v[1.4705882352941178,1.4705882352941178]
+[hierarchy_layout/gds_write_file]: Adding contact_22 boundary [v[0.0,0.0], v[0.37,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_22 boundary [v[0.0,0.0], v[0.37,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_8 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_8 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_15 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_15 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_10 boundary [v[-0.295,-0.255], v[0.545,0.585]]
+[hierarchy_layout/gds_write_file]: Adding contact_10 boundary [v[-0.295,-0.255], v[0.545,0.585]]
+[hierarchy_layout/gds_write_file]: Adding contact_11 boundary [v[-0.1,-0.1], v[0.43,0.43]]
+[hierarchy_layout/gds_write_file]: Adding contact_11 boundary [v[-0.1,-0.1], v[0.43,0.43]]
+[hierarchy_layout/gds_write_file]: Adding contact_12 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_12 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_13 boundary [v[0.0,0.0], v[0.29,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_13 boundary [v[0.0,0.0], v[0.29,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_14 boundary [v[0.0,0.0], v[0.26,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_14 boundary [v[0.0,0.0], v[0.26,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_16 boundary [v[0.0,0.0], v[0.23,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_16 boundary [v[0.0,0.0], v[0.23,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_17 boundary [v[-0.125,-0.105], v[0.375,0.435]]
+[hierarchy_layout/gds_write_file]: Adding contact_17 boundary [v[-0.125,-0.105], v[0.375,0.435]]
+[hierarchy_layout/gds_write_file]: Adding contact_18 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_18 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_19 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_19 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_7 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_7 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_20 boundary [v[0.0,0.0], v[0.33,0.23]]
+[hierarchy_layout/gds_write_file]: Adding contact_20 boundary [v[0.0,0.0], v[0.33,0.23]]
+[hierarchy_layout/gds_write_file]: Adding contact_21 boundary [v[0.0,0.0], v[0.32,0.26]]
+[hierarchy_layout/gds_write_file]: Adding contact_21 boundary [v[0.0,0.0], v[0.32,0.26]]
+[hierarchy_layout/gds_write_file]: Adding contact_24 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_24 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_25 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_25 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_26 boundary [v[0.0,0.0], v[0.33,0.29]]
+[hierarchy_layout/gds_write_file]: Adding contact_26 boundary [v[0.0,0.0], v[0.33,0.29]]
+[hierarchy_layout/gds_write_file]: Adding contact_28 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_28 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_29 boundary [v[0.0,0.0], v[0.38,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_29 boundary [v[0.0,0.0], v[0.38,0.33]]
+[hierarchy_layout/gds_write_file]: Adding sram_16_16_sky130_0.01 boundary [v[-23.18,-38.65], v[234.76,122.825]]
+[hierarchy_layout/gds_write_file]: Adding sram_16_16_sky130_0.01 boundary [v[-23.18,-38.65], v[234.76,122.825]]

compiler/sram_0.05/sram_16_16_sky130_0.05.log

@@ -0,0 +1,68 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/sram_0.05/
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+WARNING: file __init__.py: line 79: Did not find Magic.
+
+[globals/setup_bitcell]: Using bitcell: bitcell
+|==============================================================================|
+|=========                       OpenRAM v1.1.6                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 09/02/2020 02:58:03
+Technology: sky130
+Total size: 256 bits
+Word size: 16
+Words: 16
+Banks: 1
+Write size: 8
+RW ports: 1
+R-only ports: 0
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 16
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.lvs
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.sp
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.v
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.lib
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.py
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.html
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.log
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.lef
+/home/jesse/openram/compiler/sram_0.05/sram_16_16_sky130_0.05.gds
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=16
+[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
+[precharge_array/__init__]: Creating precharge_array
+[sense_amp_array/__init__]: Creating sense_amp_array
+[write_driver_array/__init__]: Creating write_driver_array
+[write_mask_and_array/__init__]: Creating write_mask_and_array
+[pand2/__init__]: Creating pand2 pand2
+[pdriver/__init__]: creating pdriver pdriver
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[bitcell_base_array/__init__]: Creating replica_bitcell_array 16 x 16
+ERROR: file vlsiLayout.py: line 609: Error: s8sram_cell_opt1.cell_size information not found yet
+

compiler/sram_0.05/sram_16_16_sky130_0.05.py

@@ -0,0 +1,27 @@
+word_size = 16
+num_words = 16
+
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "sky130"
+
+accuracy_requirement = 0.05
+magic_exe = ("magic", "magic")
+nominal_corners_only = False
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+netlist_only = False
+route_supplies = "hannan"
+check_lvsdrc = False
+
+output_path = "sram_" + str(accuracy_requirement)
+output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,
+                                        num_words,
+                                        tech_name,
+                                        accuracy_requirement
+                                        )
+write_size=8

compiler/sram_0.05/sram_16_16_sky130_0.05.v

@@ -0,0 +1,100 @@
+// OpenRAM SRAM model
+// Words: 16
+// Word size: 16
+// Write size: 8
+
+module sram_16_16_sky130_0.05(
+// Port 0: RW
+    clk0,csb0,web0,wmask0,addr0,din0,dout0,
+// Port 1: R
+    clk1,csb1,addr1,dout1
+  );
+
+  parameter NUM_WMASKS = 2 ;
+  parameter DATA_WIDTH = 16 ;
+  parameter ADDR_WIDTH = 4 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [NUM_WMASKS-1:0]   wmask0; // write mask
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+  input  clk1; // clock
+  input   csb1; // active low chip select
+  input [ADDR_WIDTH-1:0]  addr1;
+  output [DATA_WIDTH-1:0] dout1;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [NUM_WMASKS-1:0]   wmask0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    wmask0_reg = wmask0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    dout0 = 16'bx;
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
+  end
+
+  reg  csb1_reg;
+  reg [ADDR_WIDTH-1:0]  addr1_reg;
+  reg [DATA_WIDTH-1:0]  dout1;
+
+  // All inputs are registers
+  always @(posedge clk1)
+  begin
+    csb1_reg = csb1;
+    addr1_reg = addr1;
+    if (!csb0 && !web0 && !csb1 && (addr0 == addr1))
+         $display($time," WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!",addr0,addr1);
+    dout1 = 16'bx;
+    if ( !csb1_reg ) 
+      $display($time," Reading %m addr1=%b dout1=%b",addr1_reg,mem[addr1_reg]);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        if (wmask0_reg[0])
+                mem[addr0_reg][7:0] = din0_reg[7:0];
+        if (wmask0_reg[1])
+                mem[addr0_reg][15:8] = din0_reg[15:8];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+  // Memory Read Block Port 1
+  // Read Operation : When web1 = 1, csb1 = 0
+  always @ (negedge clk1)
+  begin : MEM_READ1
+    if (!csb1_reg)
+       dout1 <= #(DELAY) mem[addr1_reg];
+  end
+
+endmodule

compiler/sram_0.05/sram_16_16_sky130_0p05_FF_1p8V_25C.lib

@@ -0,0 +1,575 @@
+library (sram_16_16_sky130_0p05_FF_1p8V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 1.8 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 1.8;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 1.8 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.0017224999999999999, 0.006889999999999999, 0.027559999999999998");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.00125, 0.005, 0.04");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 16;
+    bit_from : 0;
+    bit_to : 15;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+    type (wmask){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+cell (sram_16_16_sky130_0.05){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 16;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 41174.9659;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.0006;
+    }
+    cell_leakage_power : 0.0006;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[15:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.249, 0.276, 0.38",\
+                   "0.249, 0.276, 0.38",\
+                   "0.249, 0.276, 0.38");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.249, 0.276, 0.38",\
+                   "0.249, 0.276, 0.38",\
+                   "0.249, 0.276, 0.38");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask0){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.344083e+00");
+            }
+            fall_power(scalar){
+                values("2.344083e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.344083e+00");
+            }
+            fall_power(scalar){
+                values("2.344083e+00");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.344083e+00");
+            }
+            fall_power(scalar){
+                values("2.344083e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.344083e+00");
+            }
+            fall_power(scalar){
+                values("2.344083e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.038"); 
+            }
+            fall_constraint(scalar) {
+                values("0.038"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.076"); 
+            }
+            fall_constraint(scalar) {
+                values("0.076"); 
+            }
+         }
+    }
+
+    bus(dout1){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr1; 
+        }
+        pin(dout1[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk1"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.249, 0.276, 0.38",\
+                   "0.249, 0.276, 0.38",\
+                   "0.249, 0.276, 0.38");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.249, 0.276, 0.38",\
+                   "0.249, 0.276, 0.38",\
+                   "0.249, 0.276, 0.38");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015");
+            }
+        }
+        }
+    }
+
+    bus(addr1){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr1[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask1){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask1[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb1){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk1){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb1"; 
+            rise_power(scalar){
+                values("2.344083e+00");
+            }
+            fall_power(scalar){
+                values("2.344083e+00");
+            }
+        }
+        internal_power(){
+            when : "csb1"; 
+            rise_power(scalar){
+                values("2.344083e+00");
+            }
+            fall_power(scalar){
+                values("2.344083e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.038"); 
+            }
+            fall_constraint(scalar) {
+                values("0.038"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.076"); 
+            }
+            fall_constraint(scalar) {
+                values("0.076"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_0.05/sram_16_16_sky130_0p05_SS_1p8V_25C.lib

@@ -0,0 +1,575 @@
+library (sram_16_16_sky130_0p05_SS_1p8V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 1.8 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 1.8;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 1.8 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.0017224999999999999, 0.006889999999999999, 0.027559999999999998");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.00125, 0.005, 0.04");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 16;
+    bit_from : 0;
+    bit_to : 15;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+    type (wmask){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+cell (sram_16_16_sky130_0.05){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 16;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 41174.9659;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.0006;
+    }
+    cell_leakage_power : 0.0006;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[15:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.305, 0.337, 0.465",\
+                   "0.305, 0.337, 0.465",\
+                   "0.305, 0.337, 0.465");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.305, 0.337, 0.465",\
+                   "0.305, 0.337, 0.465",\
+                   "0.305, 0.337, 0.465");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask0){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.917886e+00");
+            }
+            fall_power(scalar){
+                values("1.917886e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.917886e+00");
+            }
+            fall_power(scalar){
+                values("1.917886e+00");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("1.917886e+00");
+            }
+            fall_power(scalar){
+                values("1.917886e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("1.917886e+00");
+            }
+            fall_power(scalar){
+                values("1.917886e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.0465"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0465"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.093"); 
+            }
+            fall_constraint(scalar) {
+                values("0.093"); 
+            }
+         }
+    }
+
+    bus(dout1){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr1; 
+        }
+        pin(dout1[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk1"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.305, 0.337, 0.465",\
+                   "0.305, 0.337, 0.465",\
+                   "0.305, 0.337, 0.465");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.305, 0.337, 0.465",\
+                   "0.305, 0.337, 0.465",\
+                   "0.305, 0.337, 0.465");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018");
+            }
+        }
+        }
+    }
+
+    bus(addr1){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr1[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask1){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask1[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb1){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk1){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb1"; 
+            rise_power(scalar){
+                values("1.917886e+00");
+            }
+            fall_power(scalar){
+                values("1.917886e+00");
+            }
+        }
+        internal_power(){
+            when : "csb1"; 
+            rise_power(scalar){
+                values("1.917886e+00");
+            }
+            fall_power(scalar){
+                values("1.917886e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.0465"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0465"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.093"); 
+            }
+            fall_constraint(scalar) {
+                values("0.093"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_0.05/sram_16_16_sky130_0p05_TT_1p8V_25C.lib

@@ -0,0 +1,575 @@
+library (sram_16_16_sky130_0p05_TT_1p8V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 1.8 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 1.8;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 1.8 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.0017224999999999999, 0.006889999999999999, 0.027559999999999998");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.00125, 0.005, 0.04");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 16;
+    bit_from : 0;
+    bit_to : 15;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+    type (wmask){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+cell (sram_16_16_sky130_0.05){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 16;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 41174.9659;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.0006;
+    }
+    cell_leakage_power : 0.0006;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[15:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.277, 0.306, 0.422",\
+                   "0.277, 0.306, 0.422",\
+                   "0.277, 0.306, 0.422");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.277, 0.306, 0.422",\
+                   "0.277, 0.306, 0.422",\
+                   "0.277, 0.306, 0.422");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask0){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.109674e+00");
+            }
+            fall_power(scalar){
+                values("2.109674e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.109674e+00");
+            }
+            fall_power(scalar){
+                values("2.109674e+00");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.109674e+00");
+            }
+            fall_power(scalar){
+                values("2.109674e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.109674e+00");
+            }
+            fall_power(scalar){
+                values("2.109674e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.042"); 
+            }
+            fall_constraint(scalar) {
+                values("0.042"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.084"); 
+            }
+            fall_constraint(scalar) {
+                values("0.084"); 
+            }
+         }
+    }
+
+    bus(dout1){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr1; 
+        }
+        pin(dout1[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk1"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.277, 0.306, 0.422",\
+                   "0.277, 0.306, 0.422",\
+                   "0.277, 0.306, 0.422");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.277, 0.306, 0.422",\
+                   "0.277, 0.306, 0.422",\
+                   "0.277, 0.306, 0.422");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016");
+            }
+        }
+        }
+    }
+
+    bus(addr1){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr1[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask1){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask1[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb1){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk1){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb1"; 
+            rise_power(scalar){
+                values("2.109674e+00");
+            }
+            fall_power(scalar){
+                values("2.109674e+00");
+            }
+        }
+        internal_power(){
+            when : "csb1"; 
+            rise_power(scalar){
+                values("2.109674e+00");
+            }
+            fall_power(scalar){
+                values("2.109674e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.042"); 
+            }
+            fall_constraint(scalar) {
+                values("0.042"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.084"); 
+            }
+            fall_constraint(scalar) {
+                values("0.084"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_0.05/sram_16_16_sky130_0p05_TT_5p0V_25C.lib

@@ -0,0 +1,575 @@
+library (sram_16_16_sky130_0p05_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 1.8;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 1.8 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.0017224999999999999, 0.006889999999999999, 0.027559999999999998");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.00125, 0.005, 0.04");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 16;
+    bit_from : 0;
+    bit_to : 15;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+    type (wmask){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+cell (sram_16_16_sky130_0.05){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 16;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 41174.9659;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.0006;
+    }
+    cell_leakage_power : 0.0006;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[15:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.1, 0.11, 0.152",\
+                   "0.1, 0.11, 0.152",\
+                   "0.1, 0.11, 0.152");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.1, 0.11, 0.152",\
+                   "0.1, 0.11, 0.152",\
+                   "0.1, 0.11, 0.152");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.001, 0.002, 0.006",\
+                   "0.001, 0.002, 0.006",\
+                   "0.001, 0.002, 0.006");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.001, 0.002, 0.006",\
+                   "0.001, 0.002, 0.006",\
+                   "0.001, 0.002, 0.006");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask0){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.627835e+01");
+            }
+            fall_power(scalar){
+                values("1.627835e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.627835e+01");
+            }
+            fall_power(scalar){
+                values("1.627835e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("1.627835e+01");
+            }
+            fall_power(scalar){
+                values("1.627835e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("1.627835e+01");
+            }
+            fall_power(scalar){
+                values("1.627835e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.015"); 
+            }
+            fall_constraint(scalar) {
+                values("0.015"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.03"); 
+            }
+            fall_constraint(scalar) {
+                values("0.03"); 
+            }
+         }
+    }
+
+    bus(dout1){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr1; 
+        }
+        pin(dout1[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk1"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.1, 0.11, 0.152",\
+                   "0.1, 0.11, 0.152",\
+                   "0.1, 0.11, 0.152");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.1, 0.11, 0.152",\
+                   "0.1, 0.11, 0.152",\
+                   "0.1, 0.11, 0.152");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.001, 0.002, 0.006",\
+                   "0.001, 0.002, 0.006",\
+                   "0.001, 0.002, 0.006");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.001, 0.002, 0.006",\
+                   "0.001, 0.002, 0.006",\
+                   "0.001, 0.002, 0.006");
+            }
+        }
+        }
+    }
+
+    bus(addr1){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr1[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask1){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask1[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb1){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk1){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb1"; 
+            rise_power(scalar){
+                values("1.627835e+01");
+            }
+            fall_power(scalar){
+                values("1.627835e+01");
+            }
+        }
+        internal_power(){
+            when : "csb1"; 
+            rise_power(scalar){
+                values("1.627835e+01");
+            }
+            fall_power(scalar){
+                values("1.627835e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.015"); 
+            }
+            fall_constraint(scalar) {
+                values("0.015"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.03"); 
+            }
+            fall_constraint(scalar) {
+                values("0.03"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_0.75/sram_16_16_s8_0.75.log

@@ -0,0 +1,76 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/sram_0.75/
+[globals/import_tech]: Importing technology: s8
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: Finding DRC/LVS/PEX tools.
+[globals/get_tool]: Finding DRC tool...
+[globals/get_tool]: Using DRC: /usr/local/bin/magic
+[globals/get_tool]: Finding LVS tool...
+[globals/get_tool]: Using LVS: /usr/local/bin/netgen
+[globals/get_tool]: Finding PEX tool...
+[globals/get_tool]: Using PEX: /usr/local/bin/magic
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/25/2020 07:47:31
+Technology: s8
+Total size: 256 bits
+Word size: 16
+Words: 16
+Banks: 1
+Write size: 8
+RW ports: 1
+R-only ports: 1
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 16
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_s8_0.75.sp
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_s8_0.75.v
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_s8_0.75.lib
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_s8_0.75.py
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_s8_0.75.html
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_s8_0.75.log
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_s8_0.75.lef
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_s8_0.75.gds
+[sram/__init__]: create sram of size 16 with 16 num of words 1 banks
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=16
+[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
+[bank/__init__]: create sram of size 16 with 16 words
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge/__init__]: creating precharge cell precharge
+[precharge_array/__init__]: Creating precharge_array
+[precharge/__init__]: creating precharge cell precharge_0
+[sense_amp_array/__init__]: Creating sense_amp_array
+[sense_amp/__init__]: Create sense_amp
+[write_driver_array/__init__]: Creating write_driver_array
+[write_driver/__init__]: Create write_driver
+[write_mask_and_array/__init__]: Creating write_mask_and_array
+[pand2/__init__]: Creating pand2 pand2
+[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1
+[pdriver/__init__]: creating pdriver pdriver
+[pinv/__init__]: creating pinv structure pinv with size of 2.0
+[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000

compiler/sram_0.75/sram_16_16_sky130_0.75.log

@@ -0,0 +1,108 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/sram_0.75/
+[globals/import_tech]: Importing technology: sky130
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: Finding DRC/LVS/PEX tools.
+[globals/get_tool]: Finding DRC tool...
+[globals/get_tool]: Using DRC: /usr/local/bin/magic
+[globals/get_tool]: Finding LVS tool...
+[globals/get_tool]: Using LVS: /usr/local/bin/netgen
+[globals/get_tool]: Finding PEX tool...
+[globals/get_tool]: Using PEX: /usr/local/bin/magic
+[globals/get_tool]: Finding GDS tool...
+[globals/get_tool]: Using GDS: /usr/local/bin/magic
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/25/2020 07:50:23
+Technology: sky130
+Total size: 256 bits
+Word size: 16
+Words: 16
+Banks: 1
+Write size: 8
+RW ports: 1
+R-only ports: 1
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 16
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_sky130_0.75.sp
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_sky130_0.75.v
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_sky130_0.75.lib
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_sky130_0.75.py
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_sky130_0.75.html
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_sky130_0.75.log
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_sky130_0.75.lef
+/home/jesse/openram/compiler/sram_0.75/sram_16_16_sky130_0.75.gds
+[sram/__init__]: create sram of size 16 with 16 num of words 1 banks
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=16
+[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
+[bank/__init__]: create sram of size 16 with 16 words
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge/__init__]: creating precharge cell precharge
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
+[precharge_array/__init__]: Creating precharge_array
+[precharge/__init__]: creating precharge cell precharge_0
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
+[sense_amp_array/__init__]: Creating sense_amp_array
+[sense_amp/__init__]: Create sense_amp
+[write_driver_array/__init__]: Creating write_driver_array
+[write_driver/__init__]: Create write_driver
+[write_mask_and_array/__init__]: Creating write_mask_and_array
+[pand2/__init__]: Creating pand2 pand2
+[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pdriver/__init__]: creating pdriver pdriver
+[pinv/__init__]: creating pinv structure pinv with size of 2.0
+[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 2 pinv bin error: 1.5000000000000002 percent error 0.7500000000000001
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge_array/__init__]: Creating precharge_array_0
+[precharge/__init__]: creating precharge cell precharge_1
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 0.55 x 1 = 0.55
+[port_address/__init__]: create data port of cols 16 rows 16
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1
+[pinv/__init__]: creating pinv structure pinv_dec with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 16
+[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 16
+[pgate/bin_width]: binning nmos tx, target: 5.76, found 7.0 x 1 = 7.0
+[pgate/bin_width]: binning pmos tx, target: 17.28, found 7.0 x 3 = 21.0
+ERROR: file hierarchy_layout.py: line 278: Should use a pin iterator since more than one pin S
+
+[hierarchy_layout/gds_write_file]: Adding contact_10 boundary [v[-0.295,-0.255], v[0.545,0.585]]
+[hierarchy_layout/gds_write_file]: Adding contact_10 boundary [v[-0.295,-0.255], v[0.545,0.585]]
+ERROR: file hierarchy_layout.py: line 278: No pin found with name S on pmos_m3_w7_000_sli_dli_da_p. Saved as missing_pin.gds.
+

compiler/sram_0.78/sram_16_16_sky130_0.78.log

@@ -0,0 +1,295 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/sram_0.78/
+[globals/import_tech]: Importing technology: sky130
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/25/2020 16:59:39
+Technology: sky130
+Total size: 256 bits
+Word size: 16
+Words: 16
+Banks: 1
+Write size: 8
+RW ports: 1
+R-only ports: 1
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 16
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/sram_0.78/sram_16_16_sky130_0.78.sp
+/home/jesse/openram/compiler/sram_0.78/sram_16_16_sky130_0.78.v
+/home/jesse/openram/compiler/sram_0.78/sram_16_16_sky130_0.78.lib
+/home/jesse/openram/compiler/sram_0.78/sram_16_16_sky130_0.78.py
+/home/jesse/openram/compiler/sram_0.78/sram_16_16_sky130_0.78.html
+/home/jesse/openram/compiler/sram_0.78/sram_16_16_sky130_0.78.log
+/home/jesse/openram/compiler/sram_0.78/sram_16_16_sky130_0.78.lef
+/home/jesse/openram/compiler/sram_0.78/sram_16_16_sky130_0.78.gds
+[sram/__init__]: create sram of size 16 with 16 num of words 1 banks
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=16
+[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
+[bank/__init__]: create sram of size 16 with 16 words
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge/__init__]: creating precharge cell precharge
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning pmos tx, target: 1.26, found 1.26 x 1 = 1.26
+[precharge_array/__init__]: Creating precharge_array
+[precharge/__init__]: creating precharge cell precharge_0
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[sense_amp_array/__init__]: Creating sense_amp_array
+[sense_amp/__init__]: Create sense_amp
+[write_driver_array/__init__]: Creating write_driver_array
+[write_driver/__init__]: Create write_driver
+[write_mask_and_array/__init__]: Creating write_mask_and_array
+[pand2/__init__]: Creating pand2 pand2
+[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning nmos tx, target: 0.84, found 1.0 x 1 = 1.0
+[pgate/bin_width]: binning nmos tx, target: 0.84, found 1.0 x 1 = 1.0
+[pgate/bin_width]: binning pmos tx, target: 1.26, found 1.26 x 1 = 1.26
+[pdriver/__init__]: creating pdriver pdriver
+[pinv/__init__]: creating pinv structure pinv with size of 2.0
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.42 x 1 = 0.42
+[pgate/bin_width]: binning pmos tx, target: 0.36, found 0.42 x 1 = 0.42
+[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 2 pinv bin error: 0.06481481481481488 percent error 0.03240740740740744
+[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.26 x 1 = 1.26
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge_array/__init__]: Creating precharge_array_0
+[precharge/__init__]: creating precharge cell precharge_1
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[port_address/__init__]: create data port of cols 16 rows 16
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1
+[pinv/__init__]: creating pinv structure pinv_dec with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.42 x 1 = 0.42
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning nmos tx, target: 0.42, found 0.42 x 1 = 0.42
+[pgate/bin_width]: binning pmos tx, target: 1.26, found 1.26 x 1 = 1.26
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 16
+[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 16
+[pgate/bin_width]: binning nmos tx, target: 5.76, found 7.0 x 1 = 7.0
+[pgate/bin_width]: binning pmos tx, target: 17.28, found 7.0 x 3 = 21.0
+[pgate/bin_width]: binning nmos tx, target: 7.0, found 7.0 x 1 = 7.0
+[pgate/bin_width]: binning pmos tx, target: 7.0, found 7.0 x 1 = 7.0
+[replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 16
+[bitcell_base_array/__init__]: Creating bitcell_array 16 x 16
+[replica_bitcell_1rw_1r/__init__]: Create replica bitcell 1rw+1r object
+[dummy_bitcell_1rw_1r/__init__]: Create dummy bitcell 1rw+1r object
+[col_cap_bitcell_1rw_1r/__init__]: Create col_cap bitcell 1rw+1r object
+[bitcell_base_array/__init__]: Creating dummy_array 1 x 16
+[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16
+[bitcell_base_array/__init__]: Creating row_cap_array 20 x 1
+[row_cap_bitcell_1rw_1r/__init__]: Create row_cap bitcell 1rw+1r object
+[bitcell_base_array/__init__]: Creating row_cap_array_0 20 x 1
+[control_logic/__init__]: Creating control_logic_rw
+[dff_buf/__init__]: Creating dff_buf
+[pinv/__init__]: creating pinv structure pinv_0 with size of 2
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 4 pinv bin error: 0.12962962962962976 percent error 0.03240740740740744
+[pinv/__init__]: creating pinv structure pinv_1 with size of 4
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
+[pinv/determine_tx_mults]: pinv bin count: 6 pinv bin error: 0.44212962962962954 percent error 0.07368827160493825
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 1.6499999999999997, found 2.0 x 1 = 2.0
+[dff_buf_array/__init__]: Creating dff_buf_array
+[dff_buf/__init__]: Creating dff_buf_0
+[pand2/__init__]: Creating pand2 pand2_0
+[pnand2/__init__]: creating pnand2 structure pnand2_0 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[pdriver/__init__]: creating pdriver pdriver_0
+[pinv/__init__]: creating pinv structure pinv_2 with size of 12
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 8 pinv bin error: 0.6890432098765432 percent error 0.0861304012345679
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pbuf/__init__]: creating pbuf with size of 16
+[pinv/__init__]: creating pinv structure pinv_3 with size of 16
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: pinv bin count: 10 pinv bin error: 0.7723765432098766 percent error 0.07723765432098766
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pdriver/__init__]: creating pdriver pdriver_1
+[pinv/__init__]: creating pinv structure pinv_4 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 12 pinv bin error: 0.8094135802469137 percent error 0.0674511316872428
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.42 x 1 = 0.42
+[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.26 x 1 = 1.26
+[pinv/__init__]: creating pinv structure pinv_5 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 14 pinv bin error: 0.8464506172839508 percent error 0.06046075837742505
+[pinv/__init__]: creating pinv structure pinv_6 with size of 4
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
+[pinv/determine_tx_mults]: pinv bin count: 16 pinv bin error: 1.1589506172839505 percent error 0.07243441358024691
+[pinv/__init__]: creating pinv structure pinv_7 with size of 13
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 14.04, found 2.0 x 8 = 16.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.68, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 18 pinv bin error: 1.3754748338081673 percent error 0.07641526854489818
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pinv/__init__]: creating pinv structure pinv_8 with size of 38
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 41.04, found 2.0 x 21 = 42.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.68, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: pinv bin count: 20 pinv bin error: 1.4222584595391614 percent error 0.07111292297695807
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pdriver/__init__]: creating pdriver pdriver_2
+[pinv/__init__]: creating pinv structure pinv_9 with size of 2
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 22 pinv bin error: 1.4870732743539763 percent error 0.06759423974336255
+[pinv/__init__]: creating pinv structure pinv_10 with size of 5
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 5.3999999999999995, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.7999999999999998, found 2.0 x 1 = 2.0
+[pinv/determine_tx_mults]: pinv bin count: 24 pinv bin error: 1.7092954965761986 percent error 0.07122064569067495
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pand3/__init__]: Creating pand3 pand3
+[pnand3/__init__]: creating pnand3 structure pnand3 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning nmos tx, target: 0.84, found 1.0 x 1 = 1.0
+[pdriver/__init__]: creating pdriver pdriver_3
+[pinv/__init__]: creating pinv structure pinv_11 with size of 24
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 25.919999999999998, found 2.0 x 13 = 26.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 8.64, found 2.0 x 5 = 10.0
+[pinv/determine_tx_mults]: pinv bin count: 26 pinv bin error: 1.8697893237366925 percent error 0.07191497398987279
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pand3/__init__]: Creating pand3 pand3_0
+[pdriver/__init__]: creating pdriver pdriver_4
+[pinv/__init__]: creating pinv structure pinv_12 with size of 16
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: pinv bin count: 28 pinv bin error: 1.9531226570700257 percent error 0.06975438060964377
+[pinv/__init__]: creating pinv structure pinv_13 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 30 pinv bin error: 1.9901596941070627 percent error 0.06633865647023543
+[pnand2/__init__]: creating pnand2 structure pnand2_1 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
+[pinv/__init__]: creating pinv structure pinv_14 with size of 1
+[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 32 pinv bin error: 2.0271967311441 percent error 0.06334989784825312
+[control_logic/__init__]: Creating control_logic_r
+[dff_buf_array/__init__]: Creating dff_buf_array_0
+[pdriver/__init__]: creating pdriver pdriver_5
+[pinv/__init__]: creating pinv structure pinv_15 with size of 12
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 34 pinv bin error: 2.2741103113910133 percent error 0.06688559739385333
+[pinv/__init__]: creating pinv structure pinv_16 with size of 37
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 39.96, found 2.0 x 20 = 40.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.32, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: pinv bin count: 36 pinv bin error: 2.3261623634430655 percent error 0.06461562120675182
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+** Submodules: 1.3 seconds
+** Placement: 0.0 seconds
+[router_tech/__init__]: Track width: 0.680
+[router_tech/__init__]: Track space: 0.300
+[router_tech/__init__]: Track wire width: 0.380
+[router_tech/__init__]: Track factor: v[1.4705882352941178,1.4705882352941178]
+[hierarchy_layout/gds_write_file]: Adding contact_22 boundary [v[0.0,0.0], v[0.37,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_22 boundary [v[0.0,0.0], v[0.37,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_8 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_8 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_15 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_15 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_10 boundary [v[-0.295,-0.255], v[0.545,0.585]]
+[hierarchy_layout/gds_write_file]: Adding contact_10 boundary [v[-0.295,-0.255], v[0.545,0.585]]
+[hierarchy_layout/gds_write_file]: Adding contact_11 boundary [v[-0.1,-0.1], v[0.43,0.43]]
+[hierarchy_layout/gds_write_file]: Adding contact_11 boundary [v[-0.1,-0.1], v[0.43,0.43]]
+[hierarchy_layout/gds_write_file]: Adding contact_12 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_12 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_13 boundary [v[0.0,0.0], v[0.29,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_13 boundary [v[0.0,0.0], v[0.29,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_14 boundary [v[0.0,0.0], v[0.26,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_14 boundary [v[0.0,0.0], v[0.26,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_16 boundary [v[0.0,0.0], v[0.23,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_16 boundary [v[0.0,0.0], v[0.23,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_17 boundary [v[-0.125,-0.105], v[0.375,0.435]]
+[hierarchy_layout/gds_write_file]: Adding contact_17 boundary [v[-0.125,-0.105], v[0.375,0.435]]
+[hierarchy_layout/gds_write_file]: Adding contact_18 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_18 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_19 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_19 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_7 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_7 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_20 boundary [v[0.0,0.0], v[0.33,0.23]]
+[hierarchy_layout/gds_write_file]: Adding contact_20 boundary [v[0.0,0.0], v[0.33,0.23]]
+[hierarchy_layout/gds_write_file]: Adding contact_21 boundary [v[0.0,0.0], v[0.32,0.26]]
+[hierarchy_layout/gds_write_file]: Adding contact_21 boundary [v[0.0,0.0], v[0.32,0.26]]
+[hierarchy_layout/gds_write_file]: Adding contact_24 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_24 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_25 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_25 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_26 boundary [v[0.0,0.0], v[0.33,0.29]]
+[hierarchy_layout/gds_write_file]: Adding contact_26 boundary [v[0.0,0.0], v[0.33,0.29]]
+[hierarchy_layout/gds_write_file]: Adding contact_28 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_28 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_29 boundary [v[0.0,0.0], v[0.38,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_29 boundary [v[0.0,0.0], v[0.38,0.33]]
+[hierarchy_layout/gds_write_file]: Adding sram_16_16_sky130_0.78 boundary [v[-23.18,-38.65], v[184.84,119.345]]
+[hierarchy_layout/gds_write_file]: Adding sram_16_16_sky130_0.78 boundary [v[-23.18,-38.65], v[184.84,119.345]]

compiler/sram_0.8/sram_16_16_sky130_0.8.log

@@ -0,0 +1,295 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/sram_0.8/
+[globals/import_tech]: Importing technology: sky130
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/25/2020 17:12:03
+Technology: sky130
+Total size: 256 bits
+Word size: 16
+Words: 16
+Banks: 1
+Write size: 8
+RW ports: 1
+R-only ports: 1
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 16
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/sram_0.8/sram_16_16_sky130_0.8.sp
+/home/jesse/openram/compiler/sram_0.8/sram_16_16_sky130_0.8.v
+/home/jesse/openram/compiler/sram_0.8/sram_16_16_sky130_0.8.lib
+/home/jesse/openram/compiler/sram_0.8/sram_16_16_sky130_0.8.py
+/home/jesse/openram/compiler/sram_0.8/sram_16_16_sky130_0.8.html
+/home/jesse/openram/compiler/sram_0.8/sram_16_16_sky130_0.8.log
+/home/jesse/openram/compiler/sram_0.8/sram_16_16_sky130_0.8.lef
+/home/jesse/openram/compiler/sram_0.8/sram_16_16_sky130_0.8.gds
+[sram/__init__]: create sram of size 16 with 16 num of words 1 banks
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=16
+[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
+[bank/__init__]: create sram of size 16 with 16 words
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge/__init__]: creating precharge cell precharge
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning pmos tx, target: 1.26, found 1.26 x 1 = 1.26
+[precharge_array/__init__]: Creating precharge_array
+[precharge/__init__]: creating precharge cell precharge_0
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[sense_amp_array/__init__]: Creating sense_amp_array
+[sense_amp/__init__]: Create sense_amp
+[write_driver_array/__init__]: Creating write_driver_array
+[write_driver/__init__]: Create write_driver
+[write_mask_and_array/__init__]: Creating write_mask_and_array
+[pand2/__init__]: Creating pand2 pand2
+[pnand2/__init__]: creating pnand2 structure pnand2 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning nmos tx, target: 0.84, found 1.0 x 1 = 1.0
+[pgate/bin_width]: binning nmos tx, target: 0.84, found 1.0 x 1 = 1.0
+[pgate/bin_width]: binning pmos tx, target: 1.26, found 1.26 x 1 = 1.26
+[pdriver/__init__]: creating pdriver pdriver
+[pinv/__init__]: creating pinv structure pinv with size of 2.0
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.42 x 1 = 0.42
+[pgate/bin_width]: binning pmos tx, target: 0.36, found 0.42 x 1 = 0.42
+[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 2 pinv bin error: 0.06481481481481488 percent error 0.03240740740740744
+[pgate/bin_width]: binning nmos tx, target: 0.74, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.26 x 1 = 1.26
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge_array/__init__]: Creating precharge_array_0
+[precharge/__init__]: creating precharge cell precharge_1
+[pgate/bin_width]: binning pmos tx, target: 0.44999999999999996, found 1.26 x 1 = 1.26
+[port_address/__init__]: create data port of cols 16 rows 16
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[pinv_dec/__init__]: creating pinv_dec structure pinv_dec with size of 1
+[pinv/__init__]: creating pinv structure pinv_dec with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.42 x 1 = 0.42
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning nmos tx, target: 0.42, found 0.42 x 1 = 0.42
+[pgate/bin_width]: binning pmos tx, target: 1.26, found 1.26 x 1 = 1.26
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[pinv_dec/__init__]: creating pinv_dec structure pinv_dec_0 with size of 16
+[pinv/__init__]: creating pinv structure pinv_dec_0 with size of 16
+[pgate/bin_width]: binning nmos tx, target: 5.76, found 3.0 x 2 = 6.0
+[pgate/bin_width]: binning pmos tx, target: 17.28, found 5.0 x 4 = 20.0
+[pgate/bin_width]: binning nmos tx, target: 3.0, found 3.0 x 1 = 3.0
+[pgate/bin_width]: binning pmos tx, target: 5.0, found 5.0 x 1 = 5.0
+[replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 16
+[bitcell_base_array/__init__]: Creating bitcell_array 16 x 16
+[replica_bitcell_1rw_1r/__init__]: Create replica bitcell 1rw+1r object
+[dummy_bitcell_1rw_1r/__init__]: Create dummy bitcell 1rw+1r object
+[col_cap_bitcell_1rw_1r/__init__]: Create col_cap bitcell 1rw+1r object
+[bitcell_base_array/__init__]: Creating dummy_array 1 x 16
+[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16
+[bitcell_base_array/__init__]: Creating row_cap_array 20 x 1
+[row_cap_bitcell_1rw_1r/__init__]: Create row_cap bitcell 1rw+1r object
+[bitcell_base_array/__init__]: Creating row_cap_array_0 20 x 1
+[control_logic/__init__]: Creating control_logic_rw
+[dff_buf/__init__]: Creating dff_buf
+[pinv/__init__]: creating pinv structure pinv_0 with size of 2
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 4 pinv bin error: 0.12962962962962976 percent error 0.03240740740740744
+[pinv/__init__]: creating pinv structure pinv_1 with size of 4
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
+[pinv/determine_tx_mults]: pinv bin count: 6 pinv bin error: 0.44212962962962954 percent error 0.07368827160493825
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 1.6499999999999997, found 1.68 x 1 = 1.68
+[dff_buf_array/__init__]: Creating dff_buf_array
+[dff_buf/__init__]: Creating dff_buf_0
+[pand2/__init__]: Creating pand2 pand2_0
+[pnand2/__init__]: creating pnand2 structure pnand2_0 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[pdriver/__init__]: creating pdriver pdriver_0
+[pinv/__init__]: creating pinv structure pinv_2 with size of 12
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 8 pinv bin error: 0.6890432098765432 percent error 0.0861304012345679
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pbuf/__init__]: creating pbuf with size of 16
+[pinv/__init__]: creating pinv structure pinv_3 with size of 16
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: pinv bin count: 10 pinv bin error: 0.7723765432098766 percent error 0.07723765432098766
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pdriver/__init__]: creating pdriver pdriver_1
+[pinv/__init__]: creating pinv structure pinv_4 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 12 pinv bin error: 0.8094135802469137 percent error 0.0674511316872428
+[pgate/bin_width]: binning nmos tx, target: 0.36, found 0.42 x 1 = 0.42
+[pgate/bin_width]: binning pmos tx, target: 1.12, found 1.26 x 1 = 1.26
+[pinv/__init__]: creating pinv structure pinv_5 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 14 pinv bin error: 0.8464506172839508 percent error 0.06046075837742505
+[pinv/__init__]: creating pinv structure pinv_6 with size of 4
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 4.32, found 1.6499999999999997 x 3 = 4.949999999999999
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.44, found 1.68 x 1 = 1.68
+[pinv/determine_tx_mults]: pinv bin count: 16 pinv bin error: 1.1589506172839505 percent error 0.07243441358024691
+[pinv/__init__]: creating pinv structure pinv_7 with size of 13
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 14.04, found 2.0 x 8 = 16.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.68, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 18 pinv bin error: 1.3754748338081673 percent error 0.07641526854489818
+[pgate/bin_width]: binning nmos tx, target: 1.68, found 5.0 x 1 = 5.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pinv/__init__]: creating pinv structure pinv_8 with size of 38
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 41.04, found 2.0 x 21 = 42.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.68, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: pinv bin count: 20 pinv bin error: 1.4222584595391614 percent error 0.07111292297695807
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pdriver/__init__]: creating pdriver pdriver_2
+[pinv/__init__]: creating pinv structure pinv_9 with size of 2
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 2.16, found 1.12 x 2 = 2.24
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.72, found 0.74 x 1 = 0.74
+[pinv/determine_tx_mults]: pinv bin count: 22 pinv bin error: 1.4870732743539763 percent error 0.06759423974336255
+[pinv/__init__]: creating pinv structure pinv_10 with size of 5
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 5.3999999999999995, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 1.7999999999999998, found 2.0 x 1 = 2.0
+[pinv/determine_tx_mults]: pinv bin count: 24 pinv bin error: 1.7092954965761986 percent error 0.07122064569067495
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pand3/__init__]: Creating pand3 pand3
+[pnand3/__init__]: creating pnand3 structure pnand3 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[pgate/bin_width]: binning nmos tx, target: 0.84, found 1.0 x 1 = 1.0
+[pdriver/__init__]: creating pdriver pdriver_3
+[pinv/__init__]: creating pinv structure pinv_11 with size of 24
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 25.919999999999998, found 2.0 x 13 = 26.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 8.64, found 2.0 x 5 = 10.0
+[pinv/determine_tx_mults]: pinv bin count: 26 pinv bin error: 1.8697893237366925 percent error 0.07191497398987279
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pand3/__init__]: Creating pand3 pand3_0
+[pdriver/__init__]: creating pdriver pdriver_4
+[pinv/__init__]: creating pinv structure pinv_12 with size of 16
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 17.28, found 2.0 x 9 = 18.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 5.76, found 2.0 x 3 = 6.0
+[pinv/determine_tx_mults]: pinv bin count: 28 pinv bin error: 1.9531226570700257 percent error 0.06975438060964377
+[pinv/__init__]: creating pinv structure pinv_13 with size of 1
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 30 pinv bin error: 1.9901596941070627 percent error 0.06633865647023543
+[pnand2/__init__]: creating pnand2 structure pnand2_1 with size of 1
+[pgate/bin_width]: binning nmos tx, target: 0.72, found 0.84 x 1 = 0.84
+[pgate/bin_width]: binning pmos tx, target: 1.08, found 1.26 x 1 = 1.26
+[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
+[pinv/__init__]: creating pinv structure pinv_14 with size of 1
+[pinv/determine_tx_mults]: Height avail 4.6100 PMOS 2.2000 NMOS 2.2000
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 1.08, found 1.12 x 1 = 1.12
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 0.36, found 0.36 x 1 = 0.36
+[pinv/determine_tx_mults]: pinv bin count: 32 pinv bin error: 2.0271967311441 percent error 0.06334989784825312
+[control_logic/__init__]: Creating control_logic_r
+[dff_buf_array/__init__]: Creating dff_buf_array_0
+[pdriver/__init__]: creating pdriver pdriver_5
+[pinv/__init__]: creating pinv structure pinv_15 with size of 12
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 12.959999999999999, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 4.32, found 1.68 x 3 = 5.04
+[pinv/determine_tx_mults]: pinv bin count: 34 pinv bin error: 2.2741103113910133 percent error 0.06688559739385333
+[pinv/__init__]: creating pinv structure pinv_16 with size of 37
+[pinv/determine_tx_mults]: Height avail 6.0800 PMOS 2.9350 NMOS 2.9350
+[pinv/determine_tx_mults]: prebinning pmos tx, target: 39.96, found 2.0 x 20 = 40.0
+[pinv/determine_tx_mults]: prebinning nmos tx, target: 13.32, found 2.0 x 7 = 14.0
+[pinv/determine_tx_mults]: pinv bin count: 36 pinv bin error: 2.3261623634430655 percent error 0.06461562120675182
+[pgate/bin_width]: binning nmos tx, target: 2.0, found 2.0 x 1 = 2.0
+[pgate/bin_width]: binning pmos tx, target: 2.0, found 2.0 x 1 = 2.0
+** Submodules: 1.4 seconds
+** Placement: 0.0 seconds
+[router_tech/__init__]: Track width: 0.680
+[router_tech/__init__]: Track space: 0.300
+[router_tech/__init__]: Track wire width: 0.380
+[router_tech/__init__]: Track factor: v[1.4705882352941178,1.4705882352941178]
+[hierarchy_layout/gds_write_file]: Adding contact_22 boundary [v[0.0,0.0], v[0.37,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_22 boundary [v[0.0,0.0], v[0.37,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_8 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_8 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_15 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_15 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_10 boundary [v[-0.295,-0.255], v[0.545,0.585]]
+[hierarchy_layout/gds_write_file]: Adding contact_10 boundary [v[-0.295,-0.255], v[0.545,0.585]]
+[hierarchy_layout/gds_write_file]: Adding contact_11 boundary [v[-0.1,-0.1], v[0.43,0.43]]
+[hierarchy_layout/gds_write_file]: Adding contact_11 boundary [v[-0.1,-0.1], v[0.43,0.43]]
+[hierarchy_layout/gds_write_file]: Adding contact_12 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_12 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_13 boundary [v[0.0,0.0], v[0.29,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_13 boundary [v[0.0,0.0], v[0.29,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_14 boundary [v[0.0,0.0], v[0.26,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_14 boundary [v[0.0,0.0], v[0.26,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_16 boundary [v[0.0,0.0], v[0.23,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_16 boundary [v[0.0,0.0], v[0.23,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_17 boundary [v[-0.125,-0.105], v[0.375,0.435]]
+[hierarchy_layout/gds_write_file]: Adding contact_17 boundary [v[-0.125,-0.105], v[0.375,0.435]]
+[hierarchy_layout/gds_write_file]: Adding contact_18 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_18 boundary [v[-0.295,-0.215], v[0.545,0.625]]
+[hierarchy_layout/gds_write_file]: Adding contact_19 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_19 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_7 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_7 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_20 boundary [v[0.0,0.0], v[0.33,0.23]]
+[hierarchy_layout/gds_write_file]: Adding contact_20 boundary [v[0.0,0.0], v[0.33,0.23]]
+[hierarchy_layout/gds_write_file]: Adding contact_21 boundary [v[0.0,0.0], v[0.32,0.26]]
+[hierarchy_layout/gds_write_file]: Adding contact_21 boundary [v[0.0,0.0], v[0.32,0.26]]
+[hierarchy_layout/gds_write_file]: Adding contact_24 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_24 boundary [v[-0.125,-0.125], v[0.375,0.535]]
+[hierarchy_layout/gds_write_file]: Adding contact_25 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_25 boundary [v[0.0,0.0], v[0.32,0.32]]
+[hierarchy_layout/gds_write_file]: Adding contact_26 boundary [v[0.0,0.0], v[0.33,0.29]]
+[hierarchy_layout/gds_write_file]: Adding contact_26 boundary [v[0.0,0.0], v[0.33,0.29]]
+[hierarchy_layout/gds_write_file]: Adding contact_28 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_28 boundary [v[0.0,0.0], v[0.33,0.37]]
+[hierarchy_layout/gds_write_file]: Adding contact_29 boundary [v[0.0,0.0], v[0.38,0.33]]
+[hierarchy_layout/gds_write_file]: Adding contact_29 boundary [v[0.0,0.0], v[0.38,0.33]]
+[hierarchy_layout/gds_write_file]: Adding sram_16_16_sky130_0.8 boundary [v[-23.18,-38.65], v[172.84,119.345]]
+[hierarchy_layout/gds_write_file]: Adding sram_16_16_sky130_0.8 boundary [v[-23.18,-38.65], v[172.84,119.345]]

compiler/sram_0.85/sram_16_16_sky130_0.85.log

@@ -0,0 +1,61 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Setting up paths...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/s8config.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/sram_0.85/
+[globals/import_tech]: Importing technology: sky130
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/25/2020 17:07:21
+Technology: sky130
+Total size: 256 bits
+Word size: 16
+Words: 16
+Banks: 1
+Write size: 8
+RW ports: 1
+R-only ports: 1
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[bitcell_1rw_1r/__init__]: Create bitcell with 1RW and 1R Port
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 16
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/sram_0.85/sram_16_16_sky130_0.85.sp
+/home/jesse/openram/compiler/sram_0.85/sram_16_16_sky130_0.85.v
+/home/jesse/openram/compiler/sram_0.85/sram_16_16_sky130_0.85.lib
+/home/jesse/openram/compiler/sram_0.85/sram_16_16_sky130_0.85.py
+/home/jesse/openram/compiler/sram_0.85/sram_16_16_sky130_0.85.html
+/home/jesse/openram/compiler/sram_0.85/sram_16_16_sky130_0.85.log
+/home/jesse/openram/compiler/sram_0.85/sram_16_16_sky130_0.85.lef
+/home/jesse/openram/compiler/sram_0.85/sram_16_16_sky130_0.85.gds
+[sram/__init__]: create sram of size 16 with 16 num of words 1 banks
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=16
+[dff_array/__init__]: Creating wmask_dff rows=1 cols=2
+[bank/__init__]: create sram of size 16 with 16 words
+[port_data/__init__]: create data port of size 16 with 1 words per row
+[precharge/__init__]: creating precharge cell precharge
+ERROR: file pgate.py: line 402: failed to bin tx size 0.44999999999999996, try reducing accuracy requirement
+

compiler/sram_16_256_scn4m_subm.log

@@ -0,0 +1,138 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/run3.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/./
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/24/2020 00:32:37
+Technology: scn4m_subm
+Total size: 4096 bits
+Word size: 16
+Words: 256
+Banks: 1
+Write size: None
+RW ports: 1
+R-only ports: 0
+W-only ports: 0
+Netlist only mode (no physical design is being done, netlist_only=False to disable).
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[sram_config/recompute_sizes]: Recomputing with words per row: 4
+[sram_config/recompute_sizes]: Rows: 64 Cols: 64
+[sram_config/recompute_sizes]: Row addr size: 6 Col addr size: 2 Bank addr size: 8
+Words per row: 4
+Output files are: 
+/home/jesse/openram/compiler/./sram_16_256_scn4m_subm.sp
+/home/jesse/openram/compiler/./sram_16_256_scn4m_subm.v
+/home/jesse/openram/compiler/./sram_16_256_scn4m_subm.lib
+/home/jesse/openram/compiler/./sram_16_256_scn4m_subm.py
+/home/jesse/openram/compiler/./sram_16_256_scn4m_subm.html
+/home/jesse/openram/compiler/./sram_16_256_scn4m_subm.log
+[dff_array/__init__]: Creating row_addr_dff rows=6 cols=1
+[dff_array/__init__]: Creating col_addr_dff rows=1 cols=2
+[dff_array/__init__]: Creating data_dff rows=1 cols=16
+[precharge_array/__init__]: Creating precharge_array
+[sense_amp_array/__init__]: Creating sense_amp_array
+[single_level_column_mux_array/__init__]: Creating single_level_column_mux_array
+[write_driver_array/__init__]: Creating write_driver_array
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[replica_bitcell_array/__init__]: Creating replica_bitcell_array 64 x 64
+[bitcell_base_array/__init__]: Creating bitcell_array 64 x 64
+[bitcell_base_array/__init__]: Creating dummy_array 1 x 64
+[bitcell_base_array/__init__]: Creating dummy_array_0 67 x 1
+[bitcell_base_array/__init__]: Creating dummy_array_1 67 x 1
+[and2_dec/__init__]: Creating and2_dec and2_dec_0
+[control_logic/__init__]: Creating control_logic_rw
+[dff_buf/__init__]: Creating dff_buf
+[dff_buf_array/__init__]: Creating dff_buf_array
+[dff_buf/__init__]: Creating dff_buf_0
+[pand2/__init__]: Creating pand2 pand2
+[pdriver/__init__]: creating pdriver pdriver
+[pbuf/__init__]: creating pbuf with size of 64
+[pdriver/__init__]: creating pdriver pdriver_0
+[pdriver/__init__]: creating pdriver pdriver_1
+[pand3/__init__]: Creating pand3 pand3
+[pdriver/__init__]: creating pdriver pdriver_2
+[pand3/__init__]: Creating pand3 pand3_0
+[pdriver/__init__]: creating pdriver pdriver_3
+[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
+** Submodules: 0.4 seconds
+** SRAM creation: 0.4 seconds
+SP: Writing to /home/jesse/openram/compiler/./sram_16_256_scn4m_subm.sp
+** Spice writing: 0.0 seconds
+LIB: Characterizing... 
+[characterizer.lib/prepare_tables]: Loads: [ 2.45605  9.8242  39.2968 ]
+[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05   0.4   ]
+[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 5.0, 25), ('FF', 5.0, 25), ('SS', 5.0, 25)]
+[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_16_256_scn4m_subm_TT_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 22.978237349300006 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.004492 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.7485332297258207, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.7665821408080427, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.838777785136932, 0.015204275910518518
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.7485332297258207, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.7665821408080427, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.838777785136932, 0.015204275910518518
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.7485332297258207, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.7665821408080427, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.838777785136932, 0.015204275910518518
+[characterizer.lib/characterize_corners]: Corner: ('FF', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_16_256_scn4m_subm_FF_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 25.53137483255555 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.004492 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.473679906753239, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.4899239267272386, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.554900006623239, 0.013683848319466669
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.473679906753239, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.4899239267272386, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.554900006623239, 0.013683848319466669
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.473679906753239, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.4899239267272386, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.554900006623239, 0.013683848319466669
+[characterizer.lib/characterize_corners]: Corner: ('SS', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_16_256_scn4m_subm_SS_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 20.889306681181814 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.004492 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 3.023386552698403, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 3.0432403548888476, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 3.1226555636506252, 0.016724703501570373
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 3.023386552698403, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 3.0432403548888476, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 3.1226555636506252, 0.016724703501570373
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 3.023386552698403, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 3.0432403548888476, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 3.1226555636506252, 0.016724703501570373
+** Characterization: 0.7 seconds
+Config: Writing to /home/jesse/openram/compiler/./sram_16_256_scn4m_subm.py
+** Config: 0.0 seconds
+Datasheet: Writing to /home/jesse/openram/compiler/./sram_16_256_scn4m_subm.html
+** Datasheet: 0.0 seconds
+Verilog: Writing to /home/jesse/openram/compiler/./sram_16_256_scn4m_subm.v
+** Verilog: 0.0 seconds
+[globals/cleanup_paths]: Purging temp directory: /home/jesse/output/
+** End: 1.1 seconds

compiler/sram_16_256_scn4m_subm.py

@@ -0,0 +1,18 @@
+word_size = 16
+num_words = 256
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/sram_16_256_scn4m_subm.v

@@ -0,0 +1,61 @@
+// OpenRAM SRAM model
+// Words: 256
+// Word size: 16
+
+module sram_16_256_scn4m_subm(
+// Port 0: RW
+    clk0,csb0,web0,addr0,din0,dout0
+  );
+
+  parameter DATA_WIDTH = 16 ;
+  parameter ADDR_WIDTH = 8 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    dout0 = 16'bx;
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg )
+        mem[addr0_reg] = din0_reg;
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+endmodule

compiler/sram_16_256_scn4m_subm_FF_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_16_256_scn4m_subm_FF_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 16;
+    bit_from : 0;
+    bit_to : 15;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+cell (sram_16_256_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 8;
+    word_width : 16;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.004492;
+    }
+    cell_leakage_power : 0.004492;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[15:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("2.474, 2.49, 2.555",\
+                   "2.474, 2.49, 2.555",\
+                   "2.474, 2.49, 2.555");
+            }
+            cell_fall(CELL_TABLE) {
+            values("2.474, 2.49, 2.555",\
+                   "2.474, 2.49, 2.555",\
+                   "2.474, 2.49, 2.555");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.553137e+01");
+            }
+            fall_power(scalar){
+                values("2.553137e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.553137e+01");
+            }
+            fall_power(scalar){
+                values("2.553137e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.553137e+01");
+            }
+            fall_power(scalar){
+                values("2.553137e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.553137e+01");
+            }
+            fall_power(scalar){
+                values("2.553137e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.2555"); 
+            }
+            fall_constraint(scalar) {
+                values("0.2555"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.511"); 
+            }
+            fall_constraint(scalar) {
+                values("0.511"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_16_256_scn4m_subm_SS_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_16_256_scn4m_subm_SS_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 16;
+    bit_from : 0;
+    bit_to : 15;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+cell (sram_16_256_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 8;
+    word_width : 16;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.004492;
+    }
+    cell_leakage_power : 0.004492;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[15:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("3.023, 3.043, 3.123",\
+                   "3.023, 3.043, 3.123",\
+                   "3.023, 3.043, 3.123");
+            }
+            cell_fall(CELL_TABLE) {
+            values("3.023, 3.043, 3.123",\
+                   "3.023, 3.043, 3.123",\
+                   "3.023, 3.043, 3.123");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.088931e+01");
+            }
+            fall_power(scalar){
+                values("2.088931e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.088931e+01");
+            }
+            fall_power(scalar){
+                values("2.088931e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.088931e+01");
+            }
+            fall_power(scalar){
+                values("2.088931e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.088931e+01");
+            }
+            fall_power(scalar){
+                values("2.088931e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.3125"); 
+            }
+            fall_constraint(scalar) {
+                values("0.3125"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.625"); 
+            }
+            fall_constraint(scalar) {
+                values("0.625"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_16_256_scn4m_subm_TT_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_16_256_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 16;
+    bit_from : 0;
+    bit_to : 15;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+cell (sram_16_256_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 8;
+    word_width : 16;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.004492;
+    }
+    cell_leakage_power : 0.004492;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[15:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[15:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("2.749, 2.767, 2.839",\
+                   "2.749, 2.767, 2.839",\
+                   "2.749, 2.767, 2.839");
+            }
+            cell_fall(CELL_TABLE) {
+            values("2.749, 2.767, 2.839",\
+                   "2.749, 2.767, 2.839",\
+                   "2.749, 2.767, 2.839");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.297824e+01");
+            }
+            fall_power(scalar){
+                values("2.297824e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.297824e+01");
+            }
+            fall_power(scalar){
+                values("2.297824e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.297824e+01");
+            }
+            fall_power(scalar){
+                values("2.297824e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.297824e+01");
+            }
+            fall_power(scalar){
+                values("2.297824e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.284"); 
+            }
+            fall_constraint(scalar) {
+                values("0.284"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.568"); 
+            }
+            fall_constraint(scalar) {
+                values("0.568"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_2_16_scn4m_subm.log

@@ -0,0 +1,192 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/run1.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/./
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: Finding DRC/LVS/PEX tools.
+[globals/get_tool]: Using DRC: /usr/local/bin/magic
+[globals/get_tool]: Using LVS: /usr/local/bin/netgen
+[globals/get_tool]: Using PEX: /usr/local/bin/magic
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/24/2020 22:54:09
+Technology: scn4m_subm
+Total size: 32 bits
+Word size: 2
+Words: 16
+Banks: 1
+Write size: None
+RW ports: 1
+R-only ports: 0
+W-only ports: 0
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[sram_config/recompute_sizes]: Recomputing with words per row: 1
+[sram_config/recompute_sizes]: Rows: 16 Cols: 2
+[sram_config/recompute_sizes]: Row addr size: 4 Col addr size: 0 Bank addr size: 4
+Words per row: 1
+Output files are: 
+/home/jesse/openram/compiler/./sram_2_16_scn4m_subm.sp
+/home/jesse/openram/compiler/./sram_2_16_scn4m_subm.v
+/home/jesse/openram/compiler/./sram_2_16_scn4m_subm.lib
+/home/jesse/openram/compiler/./sram_2_16_scn4m_subm.py
+/home/jesse/openram/compiler/./sram_2_16_scn4m_subm.html
+/home/jesse/openram/compiler/./sram_2_16_scn4m_subm.log
+/home/jesse/openram/compiler/./sram_2_16_scn4m_subm.lef
+/home/jesse/openram/compiler/./sram_2_16_scn4m_subm.gds
+[dff_array/__init__]: Creating row_addr_dff rows=4 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=2
+[precharge_array/__init__]: Creating precharge_array
+[sense_amp_array/__init__]: Creating sense_amp_array
+[write_driver_array/__init__]: Creating write_driver_array
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[replica_bitcell_array/__init__]: Creating replica_bitcell_array 16 x 2
+[bitcell_base_array/__init__]: Creating bitcell_array 16 x 2
+[bitcell_base_array/__init__]: Creating dummy_array 1 x 2
+[bitcell_base_array/__init__]: Creating dummy_array_0 19 x 1
+[bitcell_base_array/__init__]: Creating dummy_array_1 19 x 1
+[control_logic/__init__]: Creating control_logic_rw
+[dff_buf/__init__]: Creating dff_buf
+[dff_buf_array/__init__]: Creating dff_buf_array
+[dff_buf/__init__]: Creating dff_buf_0
+[pand2/__init__]: Creating pand2 pand2
+[pdriver/__init__]: creating pdriver pdriver
+[pbuf/__init__]: creating pbuf with size of 2
+[pdriver/__init__]: creating pdriver pdriver_0
+[pdriver/__init__]: creating pdriver pdriver_1
+[pand3/__init__]: Creating pand3 pand3
+[pdriver/__init__]: creating pdriver pdriver_2
+[pand3/__init__]: Creating pand3 pand3_0
+[pdriver/__init__]: creating pdriver pdriver_3
+[pdriver/__init__]: creating pdriver pdriver_4
+[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
+** Submodules: 0.6 seconds
+** Placement: 0.0 seconds
+[router_tech/__init__]: Track width: 2.400
+[router_tech/__init__]: Track space: 1.200
+[router_tech/__init__]: Track wire width: 1.200
+*** Init supply router: 2.2 seconds
+[supply_grid_router/route]: Running supply router on vdd and gnd...
+[supply_grid_router/create_routing_grid]: Size: 215.7 x 423.2
+**** Retrieving pins: 0.0 seconds
+**** Analyzing pins: 0.0 seconds
+[router/find_blockages]: Finding blockages.
+**** Finding blockages: 0.1 seconds
+[router/convert_blockages]: Converting blockages.
+**** Converting blockages: 0.0 seconds
+[router/convert_pins]: Converting pins for vdd.
+[router/convert_pins]: Converting pins for gnd.
+**** Converting pins: 0.4 seconds
+[router/separate_adjacent_pin]: Comparing vdd and gnd adjacency
+[router/separate_adjacent_pin]: Removed 0 adjacent grids.
+**** Separating adjacent pins: 0.1 seconds
+[router/enclose_pins]: Enclosing pins for vdd
+[router/enclose_pins]: Enclosing pins for gnd
+**** Enclosing pins: 0.2 seconds
+*** Finding pins and blockages: 0.8 seconds
+[supply_grid_router/route_supply_rails]: Routing supply rail gnd.
+[supply_grid_router/route_supply_rails]: Routing supply rail vdd.
+*** Routing supply rails: 1.2 seconds
+[supply_grid_router/route_simple_overlaps]: Routing simple overlap pins for vdd
+[supply_grid_router/route_simple_overlaps]: Routed 102 simple overlap pins
+[supply_grid_router/route_simple_overlaps]: Routing simple overlap pins for gnd
+[supply_grid_router/route_simple_overlaps]: Routed 173 simple overlap pins
+*** Simple overlap routing: 0.0 seconds
+[supply_grid_router/route_pins_to_rails]: Maze routing vdd with 0 pin components to connect.
+[supply_grid_router/route_pins_to_rails]: Maze routing gnd with 1 pin components to connect.
+[router/run_router]: Found path: cost=3 
+[router/run_router]: [[v3d[-6, 145, 0]], [v3d[-6, 145, 1]], [v3d[-6, 144, 1]]]
+*** Maze routing supplies: 0.5 seconds
+** Routing: 4.7 seconds
+[verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm	0
+[verify.magic/run_lvs]: sram_2_16_scn4m_subm	LVS matches
+** Verification: 7.7 seconds
+** SRAM creation: 13.1 seconds
+LEF: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.lef
+** LEF: 0.4 seconds
+GDS: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.gds
+** GDS: 0.2 seconds
+SP: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.sp
+** Spice writing: 0.1 seconds
+LIB: Characterizing... 
+[characterizer.lib/prepare_tables]: Loads: [ 2.45605  9.8242  39.2968 ]
+[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05   0.4   ]
+[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 5.0, 25), ('SS', 5.0, 25), ('FF', 5.0, 25)]
+[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm_TT_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 7.041373912099999 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.000194 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 1.3470349836940743, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 1.3650838947762967, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 1.4372795391051854, 0.015204275910518518
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 1.3470349836940743, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 1.3650838947762967, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 1.4372795391051854, 0.015204275910518518
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 1.3470349836940743, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 1.3650838947762967, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 1.4372795391051854, 0.015204275910518518
+[verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm	0
+[verify.magic/run_lvs]: sram_2_16_scn4m_subm	LVS matches
+[characterizer.lib/characterize_corners]: Corner: ('SS', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm_SS_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 6.401249010999999 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.000194 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 1.481738482063482, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 1.5015922842539264, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 1.581007493015704, 0.016724703501570373
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 1.481738482063482, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 1.5015922842539264, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 1.581007493015704, 0.016724703501570373
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 1.481738482063482, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 1.5015922842539264, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 1.581007493015704, 0.016724703501570373
+[verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm	0
+[verify.magic/run_lvs]: sram_2_16_scn4m_subm	LVS matches
+[characterizer.lib/characterize_corners]: Corner: ('FF', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm_FF_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 7.82374879122222 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.000194 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 1.212331485324667, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 1.2285755052986669, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 1.293551585194667, 0.013683848319466669
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 1.212331485324667, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 1.2285755052986669, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 1.293551585194667, 0.013683848319466669
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 1.212331485324667, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 1.2285755052986669, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 1.293551585194667, 0.013683848319466669
+[verify.magic/run_drc]: DRC Errors sram_2_16_scn4m_subm	0
+[verify.magic/run_lvs]: sram_2_16_scn4m_subm	LVS matches
+** Characterization: 24.0 seconds
+Config: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.py
+** Config: 0.0 seconds
+Datasheet: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.html
+** Datasheet: 0.0 seconds
+Verilog: Writing to /home/jesse/openram/compiler/./sram_2_16_scn4m_subm.v
+** Verilog: 0.0 seconds
+[globals/cleanup_paths]: Purging temp directory: /home/jesse/output/
+[verify.magic/print_drc_stats]: DRC runs: 4
+[verify.magic/print_lvs_stats]: LVS runs: 4
+[verify.magic/print_pex_stats]: PEX runs: 0
+** End: 37.8 seconds

compiler/sram_2_16_scn4m_subm.py

@@ -0,0 +1,19 @@
+word_size = 2
+num_words = 16
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+#netlist_only = True
+route_supplies = True
+check_lvsdrc = True
+
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/sram_2_16_scn4m_subm.v

@@ -0,0 +1,61 @@
+// OpenRAM SRAM model
+// Words: 16
+// Word size: 2
+
+module sram_2_16_scn4m_subm(
+// Port 0: RW
+    clk0,csb0,web0,addr0,din0,dout0
+  );
+
+  parameter DATA_WIDTH = 2 ;
+  parameter ADDR_WIDTH = 4 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    dout0 = 2'bx;
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg )
+        mem[addr0_reg] = din0_reg;
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+endmodule

compiler/sram_2_16_scn4m_subm_FF_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_2_16_scn4m_subm_FF_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_2_16_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 2;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 91878.84000000001;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.000194;
+    }
+    cell_leakage_power : 0.000194;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[1:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("1.212, 1.229, 1.294",\
+                   "1.212, 1.229, 1.294",\
+                   "1.212, 1.229, 1.294");
+            }
+            cell_fall(CELL_TABLE) {
+            values("1.212, 1.229, 1.294",\
+                   "1.212, 1.229, 1.294",\
+                   "1.212, 1.229, 1.294");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("7.823749e+00");
+            }
+            fall_power(scalar){
+                values("7.823749e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("7.823749e+00");
+            }
+            fall_power(scalar){
+                values("7.823749e+00");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("7.823749e+00");
+            }
+            fall_power(scalar){
+                values("7.823749e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("7.823749e+00");
+            }
+            fall_power(scalar){
+                values("7.823749e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.1295"); 
+            }
+            fall_constraint(scalar) {
+                values("0.1295"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.259"); 
+            }
+            fall_constraint(scalar) {
+                values("0.259"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_2_16_scn4m_subm_SS_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_2_16_scn4m_subm_SS_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_2_16_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 2;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 91878.84000000001;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.000194;
+    }
+    cell_leakage_power : 0.000194;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[1:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("1.482, 1.502, 1.581",\
+                   "1.482, 1.502, 1.581",\
+                   "1.482, 1.502, 1.581");
+            }
+            cell_fall(CELL_TABLE) {
+            values("1.482, 1.502, 1.581",\
+                   "1.482, 1.502, 1.581",\
+                   "1.482, 1.502, 1.581");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("6.401249e+00");
+            }
+            fall_power(scalar){
+                values("6.401249e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("6.401249e+00");
+            }
+            fall_power(scalar){
+                values("6.401249e+00");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("6.401249e+00");
+            }
+            fall_power(scalar){
+                values("6.401249e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("6.401249e+00");
+            }
+            fall_power(scalar){
+                values("6.401249e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.158"); 
+            }
+            fall_constraint(scalar) {
+                values("0.158"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.316"); 
+            }
+            fall_constraint(scalar) {
+                values("0.316"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_2_16_scn4m_subm_TT_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_2_16_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_2_16_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 2;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 91878.84000000001;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.000194;
+    }
+    cell_leakage_power : 0.000194;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[1:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("1.347, 1.365, 1.437",\
+                   "1.347, 1.365, 1.437",\
+                   "1.347, 1.365, 1.437");
+            }
+            cell_fall(CELL_TABLE) {
+            values("1.347, 1.365, 1.437",\
+                   "1.347, 1.365, 1.437",\
+                   "1.347, 1.365, 1.437");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("7.041374e+00");
+            }
+            fall_power(scalar){
+                values("7.041374e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("7.041374e+00");
+            }
+            fall_power(scalar){
+                values("7.041374e+00");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("7.041374e+00");
+            }
+            fall_power(scalar){
+                values("7.041374e+00");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("7.041374e+00");
+            }
+            fall_power(scalar){
+                values("7.041374e+00");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.1435"); 
+            }
+            fall_constraint(scalar) {
+                values("0.1435"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.287"); 
+            }
+            fall_constraint(scalar) {
+                values("0.287"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_32_128_scn4m_subm.log

@@ -0,0 +1,138 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/run4.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/./
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/24/2020 00:47:16
+Technology: scn4m_subm
+Total size: 4096 bits
+Word size: 32
+Words: 128
+Banks: 1
+Write size: None
+RW ports: 1
+R-only ports: 0
+W-only ports: 0
+Netlist only mode (no physical design is being done, netlist_only=False to disable).
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[sram_config/recompute_sizes]: Recomputing with words per row: 2
+[sram_config/recompute_sizes]: Rows: 64 Cols: 64
+[sram_config/recompute_sizes]: Row addr size: 6 Col addr size: 1 Bank addr size: 7
+Words per row: 2
+Output files are: 
+/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.sp
+/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.v
+/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.lib
+/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.py
+/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.html
+/home/jesse/openram/compiler/./sram_32_128_scn4m_subm.log
+[dff_array/__init__]: Creating row_addr_dff rows=6 cols=1
+[dff_array/__init__]: Creating col_addr_dff rows=1 cols=1
+[dff_array/__init__]: Creating data_dff rows=1 cols=32
+[precharge_array/__init__]: Creating precharge_array
+[sense_amp_array/__init__]: Creating sense_amp_array
+[single_level_column_mux_array/__init__]: Creating single_level_column_mux_array
+[write_driver_array/__init__]: Creating write_driver_array
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[replica_bitcell_array/__init__]: Creating replica_bitcell_array 64 x 64
+[bitcell_base_array/__init__]: Creating bitcell_array 64 x 64
+[bitcell_base_array/__init__]: Creating dummy_array 1 x 64
+[bitcell_base_array/__init__]: Creating dummy_array_0 67 x 1
+[bitcell_base_array/__init__]: Creating dummy_array_1 67 x 1
+[pinvbuf/__init__]: creating pinvbuf pinvbuf
+[control_logic/__init__]: Creating control_logic_rw
+[dff_buf/__init__]: Creating dff_buf
+[dff_buf_array/__init__]: Creating dff_buf_array
+[dff_buf/__init__]: Creating dff_buf_0
+[pand2/__init__]: Creating pand2 pand2
+[pdriver/__init__]: creating pdriver pdriver
+[pbuf/__init__]: creating pbuf with size of 64
+[pdriver/__init__]: creating pdriver pdriver_0
+[pdriver/__init__]: creating pdriver pdriver_1
+[pand3/__init__]: Creating pand3 pand3
+[pdriver/__init__]: creating pdriver pdriver_2
+[pand3/__init__]: Creating pand3 pand3_0
+[pdriver/__init__]: creating pdriver pdriver_3
+[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
+** Submodules: 0.3 seconds
+** SRAM creation: 0.3 seconds
+SP: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm.sp
+** Spice writing: 0.0 seconds
+LIB: Characterizing... 
+[characterizer.lib/prepare_tables]: Loads: [ 2.45605  9.8242  39.2968 ]
+[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05   0.4   ]
+[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 5.0, 25), ('SS', 5.0, 25), ('FF', 5.0, 25)]
+[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm_TT_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 23.657191349300003 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.004501 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.754780008429524, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.7728289195117464, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.8450245638406355, 0.015204275910518518
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.754780008429524, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.7728289195117464, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.8450245638406355, 0.015204275910518518
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.754780008429524, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.7728289195117464, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.8450245638406355, 0.015204275910518518
+[characterizer.lib/characterize_corners]: Corner: ('SS', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm_SS_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 21.50653759027272 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.004501 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 3.030258009272477, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 3.0501118114629215, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 3.129527020224699, 0.016724703501570373
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 3.030258009272477, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 3.0501118114629215, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 3.129527020224699, 0.016724703501570373
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 3.030258009272477, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 3.0501118114629215, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 3.129527020224699, 0.016724703501570373
+[characterizer.lib/characterize_corners]: Corner: ('FF', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm_FF_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 26.285768165888882 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.004501 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.4793020075865724, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.4955460275605725, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.5605221074565723, 0.013683848319466669
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.4793020075865724, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.4955460275605725, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.5605221074565723, 0.013683848319466669
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.4793020075865724, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.4955460275605725, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.5605221074565723, 0.013683848319466669
+** Characterization: 0.6 seconds
+Config: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm.py
+** Config: 0.0 seconds
+Datasheet: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm.html
+** Datasheet: 0.0 seconds
+Verilog: Writing to /home/jesse/openram/compiler/./sram_32_128_scn4m_subm.v
+** Verilog: 0.0 seconds
+[globals/cleanup_paths]: Purging temp directory: /home/jesse/output/
+** End: 0.9 seconds

compiler/sram_32_128_scn4m_subm.py

@@ -0,0 +1,18 @@
+word_size = 32
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/sram_32_128_scn4m_subm.v

@@ -0,0 +1,61 @@
+// OpenRAM SRAM model
+// Words: 128
+// Word size: 32
+
+module sram_32_128_scn4m_subm(
+// Port 0: RW
+    clk0,csb0,web0,addr0,din0,dout0
+  );
+
+  parameter DATA_WIDTH = 32 ;
+  parameter ADDR_WIDTH = 7 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    dout0 = 32'bx;
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg )
+        mem[addr0_reg] = din0_reg;
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+endmodule

compiler/sram_32_128_scn4m_subm_FF_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_32_128_scn4m_subm_FF_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 32;
+    bit_from : 0;
+    bit_to : 31;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 7;
+    bit_from : 0;
+    bit_to : 6;
+    }
+
+cell (sram_32_128_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 7;
+    word_width : 32;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.004501;
+    }
+    cell_leakage_power : 0.004501;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[31:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("2.479, 2.496, 2.561",\
+                   "2.479, 2.496, 2.561",\
+                   "2.479, 2.496, 2.561");
+            }
+            cell_fall(CELL_TABLE) {
+            values("2.479, 2.496, 2.561",\
+                   "2.479, 2.496, 2.561",\
+                   "2.479, 2.496, 2.561");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[6:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.628577e+01");
+            }
+            fall_power(scalar){
+                values("2.628577e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.628577e+01");
+            }
+            fall_power(scalar){
+                values("2.628577e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.628577e+01");
+            }
+            fall_power(scalar){
+                values("2.628577e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.628577e+01");
+            }
+            fall_power(scalar){
+                values("2.628577e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.256"); 
+            }
+            fall_constraint(scalar) {
+                values("0.256"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.512"); 
+            }
+            fall_constraint(scalar) {
+                values("0.512"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_32_128_scn4m_subm_SS_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_32_128_scn4m_subm_SS_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 32;
+    bit_from : 0;
+    bit_to : 31;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 7;
+    bit_from : 0;
+    bit_to : 6;
+    }
+
+cell (sram_32_128_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 7;
+    word_width : 32;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.004501;
+    }
+    cell_leakage_power : 0.004501;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[31:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("3.03, 3.05, 3.13",\
+                   "3.03, 3.05, 3.13",\
+                   "3.03, 3.05, 3.13");
+            }
+            cell_fall(CELL_TABLE) {
+            values("3.03, 3.05, 3.13",\
+                   "3.03, 3.05, 3.13",\
+                   "3.03, 3.05, 3.13");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[6:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.150654e+01");
+            }
+            fall_power(scalar){
+                values("2.150654e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.150654e+01");
+            }
+            fall_power(scalar){
+                values("2.150654e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.150654e+01");
+            }
+            fall_power(scalar){
+                values("2.150654e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.150654e+01");
+            }
+            fall_power(scalar){
+                values("2.150654e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.313"); 
+            }
+            fall_constraint(scalar) {
+                values("0.313"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.626"); 
+            }
+            fall_constraint(scalar) {
+                values("0.626"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_32_128_scn4m_subm_TT_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_32_128_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 32;
+    bit_from : 0;
+    bit_to : 31;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 7;
+    bit_from : 0;
+    bit_to : 6;
+    }
+
+cell (sram_32_128_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 7;
+    word_width : 32;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.004501;
+    }
+    cell_leakage_power : 0.004501;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[31:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("2.755, 2.773, 2.845",\
+                   "2.755, 2.773, 2.845",\
+                   "2.755, 2.773, 2.845");
+            }
+            cell_fall(CELL_TABLE) {
+            values("2.755, 2.773, 2.845",\
+                   "2.755, 2.773, 2.845",\
+                   "2.755, 2.773, 2.845");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[6:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.365719e+01");
+            }
+            fall_power(scalar){
+                values("2.365719e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.365719e+01");
+            }
+            fall_power(scalar){
+                values("2.365719e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.365719e+01");
+            }
+            fall_power(scalar){
+                values("2.365719e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.365719e+01");
+            }
+            fall_power(scalar){
+                values("2.365719e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.2845"); 
+            }
+            fall_constraint(scalar) {
+                values("0.2845"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.569"); 
+            }
+            fall_constraint(scalar) {
+                values("0.569"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_8_128_scn4m_subm.log

@@ -0,0 +1,138 @@
+[globals/init_openram]: Initializing OpenRAM...
+[globals/setup_paths]: Temporary files saved in /home/jesse/output/
+[globals/read_config]: Configuration file is /home/jesse/openram/compiler/example_configs/run2.py
+[globals/read_config]: Output saved in /home/jesse/openram/compiler/./
+[globals/import_tech]: Adding technology path: /home/jesse/openram/technology
+[globals/init_paths]: Creating temp directory: /home/jesse/output/
+[verify/<module>]: Initializing verify...
+[verify/<module>]: LVS/DRC/PEX disabled.
+[characterizer/<module>]: Initializing characterizer...
+[characterizer/<module>]: Analytical model enabled.
+[globals/setup_bitcell]: Using bitcell: bitcell
+|==============================================================================|
+|=========                       OpenRAM v1.1.5                       =========|
+|=========                                                            =========|
+|=========               VLSI Design and Automation Lab               =========|
+|=========        Computer Science and Engineering Department         =========|
+|=========            University of California Santa Cruz             =========|
+|=========                                                            =========|
+|=========          Usage help: openram-user-group@ucsc.edu           =========|
+|=========        Development help: openram-dev-group@ucsc.edu        =========|
+|=========               Temp dir: /home/jesse/output/                =========|
+|=========                See LICENSE for license info                =========|
+|==============================================================================|
+** Start: 06/24/2020 00:31:44
+Technology: scn4m_subm
+Total size: 1024 bits
+Word size: 8
+Words: 128
+Banks: 1
+Write size: None
+RW ports: 1
+R-only ports: 0
+W-only ports: 0
+Netlist only mode (no physical design is being done, netlist_only=False to disable).
+DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
+DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
+Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
+[sram_config/recompute_sizes]: Recomputing with words per row: 4
+[sram_config/recompute_sizes]: Rows: 32 Cols: 32
+[sram_config/recompute_sizes]: Row addr size: 5 Col addr size: 2 Bank addr size: 7
+Words per row: 4
+Output files are: 
+/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.sp
+/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.v
+/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.lib
+/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.py
+/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.html
+/home/jesse/openram/compiler/./sram_8_128_scn4m_subm.log
+[dff_array/__init__]: Creating row_addr_dff rows=5 cols=1
+[dff_array/__init__]: Creating col_addr_dff rows=1 cols=2
+[dff_array/__init__]: Creating data_dff rows=1 cols=8
+[precharge_array/__init__]: Creating precharge_array
+[sense_amp_array/__init__]: Creating sense_amp_array
+[single_level_column_mux_array/__init__]: Creating single_level_column_mux_array
+[write_driver_array/__init__]: Creating write_driver_array
+[and2_dec/__init__]: Creating and2_dec and2_dec
+[and3_dec/__init__]: Creating and3_dec and3_dec
+[wordline_driver_array/__init__]: Creating wordline_driver_array
+[wordline_driver/__init__]: Creating wordline_driver wordline_driver
+[replica_bitcell_array/__init__]: Creating replica_bitcell_array 32 x 32
+[bitcell_base_array/__init__]: Creating bitcell_array 32 x 32
+[bitcell_base_array/__init__]: Creating dummy_array 1 x 32
+[bitcell_base_array/__init__]: Creating dummy_array_0 35 x 1
+[bitcell_base_array/__init__]: Creating dummy_array_1 35 x 1
+[and2_dec/__init__]: Creating and2_dec and2_dec_0
+[control_logic/__init__]: Creating control_logic_rw
+[dff_buf/__init__]: Creating dff_buf
+[dff_buf_array/__init__]: Creating dff_buf_array
+[dff_buf/__init__]: Creating dff_buf_0
+[pand2/__init__]: Creating pand2 pand2
+[pdriver/__init__]: creating pdriver pdriver
+[pbuf/__init__]: creating pbuf with size of 32
+[pdriver/__init__]: creating pdriver pdriver_0
+[pdriver/__init__]: creating pdriver pdriver_1
+[pand3/__init__]: Creating pand3 pand3
+[pdriver/__init__]: creating pdriver pdriver_2
+[pand3/__init__]: Creating pand3 pand3_0
+[pdriver/__init__]: creating pdriver pdriver_3
+[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4]
+** Submodules: 0.2 seconds
+** SRAM creation: 0.2 seconds
+SP: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm.sp
+** Spice writing: 0.0 seconds
+LIB: Characterizing... 
+[characterizer.lib/prepare_tables]: Loads: [ 2.45605  9.8242  39.2968 ]
+[characterizer.lib/prepare_tables]: Slews: [0.0125 0.05   0.4   ]
+[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 5.0, 25), ('FF', 5.0, 25), ('SS', 5.0, 25)]
+[characterizer.lib/characterize_corners]: Corner: ('TT', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm_TT_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 12.381903810499999 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.001282 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.1528469533910437, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.170895864473266, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.2430915088021552, 0.015204275910518518
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.1528469533910437, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.170895864473266, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.2430915088021552, 0.015204275910518518
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.1528469533910437, 0.006179820369407407
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.170895864473266, 0.00798471147762963
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.2430915088021552, 0.015204275910518518
+[characterizer.lib/characterize_corners]: Corner: ('FF', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm_FF_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 13.757670900555558 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.001282 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 1.9375622580519398, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 1.9538062780259398, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.01878235792194, 0.013683848319466669
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 1.9375622580519398, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 1.9538062780259398, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.01878235792194, 0.013683848319466669
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 1.9375622580519398, 0.0055618383324666665
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 1.9538062780259398, 0.007186240329866667
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.01878235792194, 0.013683848319466669
+[characterizer.lib/characterize_corners]: Corner: ('SS', 5.0, 25)
+[characterizer.lib/characterize_corners]: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm_SS_5p0V_25C.lib
+[characterizer.delay/analytical_power]: Dynamic Power: 11.256276191363632 mW
+[characterizer.delay/analytical_power]: Leakage Power: 0.001282 mW
+[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns)
+[characterizer.delay/analytical_delay]: 0.0125, 2.45605, 2.3681316487301483, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.0125, 9.8242, 2.387985450920593, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.0125, 39.2968, 2.4674006596823705, 0.016724703501570373
+[characterizer.delay/analytical_delay]: 0.05, 2.45605, 2.3681316487301483, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.05, 9.8242, 2.387985450920593, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.05, 39.2968, 2.4674006596823705, 0.016724703501570373
+[characterizer.delay/analytical_delay]: 0.4, 2.45605, 2.3681316487301483, 0.006797802406348149
+[characterizer.delay/analytical_delay]: 0.4, 9.8242, 2.387985450920593, 0.008783182625392592
+[characterizer.delay/analytical_delay]: 0.4, 39.2968, 2.4674006596823705, 0.016724703501570373
+** Characterization: 0.3 seconds
+Config: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm.py
+** Config: 0.0 seconds
+Datasheet: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm.html
+** Datasheet: 0.0 seconds
+Verilog: Writing to /home/jesse/openram/compiler/./sram_8_128_scn4m_subm.v
+** Verilog: 0.0 seconds
+[globals/cleanup_paths]: Purging temp directory: /home/jesse/output/
+** End: 0.5 seconds

compiler/sram_8_128_scn4m_subm.py

@@ -0,0 +1,19 @@
+word_size = 8
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+
+netlist_only = True
+output_name = "sram_{0}_{1}_{2}".format(word_size,
+                                        num_words,
+                                        tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/sram_8_128_scn4m_subm.v

@@ -0,0 +1,61 @@
+// OpenRAM SRAM model
+// Words: 128
+// Word size: 8
+
+module sram_8_128_scn4m_subm(
+// Port 0: RW
+    clk0,csb0,web0,addr0,din0,dout0
+  );
+
+  parameter DATA_WIDTH = 8 ;
+  parameter ADDR_WIDTH = 7 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    dout0 = 8'bx;
+    if ( !csb0_reg && web0_reg ) 
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg )
+      $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
+  end
+
+reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg )
+        mem[addr0_reg] = din0_reg;
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+endmodule

compiler/sram_8_128_scn4m_subm_FF_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_8_128_scn4m_subm_FF_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 7;
+    bit_from : 0;
+    bit_to : 6;
+    }
+
+cell (sram_8_128_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 7;
+    word_width : 8;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.001282;
+    }
+    cell_leakage_power : 0.001282;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[7:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("1.938, 1.954, 2.019",\
+                   "1.938, 1.954, 2.019",\
+                   "1.938, 1.954, 2.019");
+            }
+            cell_fall(CELL_TABLE) {
+            values("1.938, 1.954, 2.019",\
+                   "1.938, 1.954, 2.019",\
+                   "1.938, 1.954, 2.019");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014",\
+                   "0.006, 0.007, 0.014");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[6:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.375767e+01");
+            }
+            fall_power(scalar){
+                values("1.375767e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.375767e+01");
+            }
+            fall_power(scalar){
+                values("1.375767e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("1.375767e+01");
+            }
+            fall_power(scalar){
+                values("1.375767e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("1.375767e+01");
+            }
+            fall_power(scalar){
+                values("1.375767e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.202"); 
+            }
+            fall_constraint(scalar) {
+                values("0.202"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.404"); 
+            }
+            fall_constraint(scalar) {
+                values("0.404"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_8_128_scn4m_subm_SS_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_8_128_scn4m_subm_SS_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 7;
+    bit_from : 0;
+    bit_to : 6;
+    }
+
+cell (sram_8_128_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 7;
+    word_width : 8;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.001282;
+    }
+    cell_leakage_power : 0.001282;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[7:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("2.368, 2.388, 2.467",\
+                   "2.368, 2.388, 2.467",\
+                   "2.368, 2.388, 2.467");
+            }
+            cell_fall(CELL_TABLE) {
+            values("2.368, 2.388, 2.467",\
+                   "2.368, 2.388, 2.467",\
+                   "2.368, 2.388, 2.467");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017",\
+                   "0.007, 0.009, 0.017");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[6:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.125628e+01");
+            }
+            fall_power(scalar){
+                values("1.125628e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.125628e+01");
+            }
+            fall_power(scalar){
+                values("1.125628e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("1.125628e+01");
+            }
+            fall_power(scalar){
+                values("1.125628e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("1.125628e+01");
+            }
+            fall_power(scalar){
+                values("1.125628e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.2465"); 
+            }
+            fall_constraint(scalar) {
+                values("0.2465"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.493"); 
+            }
+            fall_constraint(scalar) {
+                values("0.493"); 
+            }
+         }
+    }
+
+    }
+}

compiler/sram_8_128_scn4m_subm_TT_5p0V_25C.lib

@@ -0,0 +1,342 @@
+library (sram_8_128_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 5.0 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.00245605, 0.0098242, 0.0392968");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 7;
+    bit_from : 0;
+    bit_to : 6;
+    }
+
+cell (sram_8_128_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 7;
+    word_width : 8;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 0;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.001282;
+    }
+    cell_leakage_power : 0.001282;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.0392968;  
+        min_capacitance : 0.00245605;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[7:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("2.153, 2.171, 2.243",\
+                   "2.153, 2.171, 2.243",\
+                   "2.153, 2.171, 2.243");
+            }
+            cell_fall(CELL_TABLE) {
+            values("2.153, 2.171, 2.243",\
+                   "2.153, 2.171, 2.243",\
+                   "2.153, 2.171, 2.243");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015",\
+                   "0.006, 0.008, 0.015");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.0098242;  
+        max_transition       : 0.4;
+        pin(addr0[6:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.0098242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.0098242;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.238190e+01");
+            }
+            fall_power(scalar){
+                values("1.238190e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.238190e+01");
+            }
+            fall_power(scalar){
+                values("1.238190e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("1.238190e+01");
+            }
+            fall_power(scalar){
+                values("1.238190e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("1.238190e+01");
+            }
+            fall_power(scalar){
+                values("1.238190e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.2245"); 
+            }
+            fall_constraint(scalar) {
+                values("0.2245"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.449"); 
+            }
+            fall_constraint(scalar) {
+                values("0.449"); 
+            }
+         }
+    }
+
+    }
+}