luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Separate route conditions for s8

This commit is contained in:
mrg 2020-06-15 10:30:27 -07:00
parent e331d6fae8
commit abb5ff7bae
2 changed files with 7 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
compiler/modules/hierarchical_decoder.py
View File

@ -11,7 +11,6 @@ import math
from sram_factory import factory
from vector import vector
from globals import OPTS
from errors import drc_error
class hierarchical_decoder(design.design):

15
compiler/modules/hierarchical_predecode.py
View File

@ -234,19 +234,18 @@ class hierarchical_predecode(design.design):
in_pin = "in_{}".format(inv_num)
inv_out_pin = self.inv_inst[inv_num].get_pin("Z")
inv_out_pos = inv_out_pin.lr()
# add output so that it is just below the vdd or gnd rail
# since this is where the p/n devices are and there are no
# pins in the and gates.
if False and OPTS.tech_name == "sky130":
rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y)
self.add_path(self.output_layer, [inv_out_pos, rail_pos])
if OPTS.tech_name == "sky130":
inv_out_pos = inv_out_pin.lr()
else:
y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch
right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0)
rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset)
self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
inv_out_pos = inv_out_pin.rc()
y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch
right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0)
rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset)
self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
self.add_via_stack_center(from_layer=inv_out_pin.layer,
to_layer=self.output_layer,