Fixes to replica bitline array.

Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting

compiler/modules/bitcell_base_array.py

@@ -56,8 +56,8 @@ class bitcell_base_array(design.design):
     # def get_all_wordline_names(self, prefix=""):
     #     return [prefix + x for x in self.all_wordline_names]
 
-    def create_all_wordline_names(self, remove_wordline = 0):
-        for row in range(self.row_size - remove_wordline):
+    def create_all_wordline_names(self, num_remove_wordline=0):
+        for row in range(self.row_size - num_remove_wordline):
             for port in self.all_ports:
                 if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
                     self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
@@ -245,4 +245,4 @@ class bitcell_base_array(design.design):
         Return an array of the x offsets of all the regular bits
         """
         offsets = [self.cell_inst[0, col].lx() for col in range(self.column_size)]
-        return offsets
+        return offsets

compiler/modules/replica_bitcell_array.py

@@ -427,7 +427,10 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
 
     def add_replica_columns(self):
         """ Add replica columns on left and right of array """
-        end_caps_enabled = cell_properties.bitcell.end_caps
+        try:
+            end_caps_enabled = cell_properties.bitcell.end_caps
+        except AttributeError:
+            end_caps_enabled = False
 
         # Grow from left to right, toward the array
         for bit, port in enumerate(self.left_rbl):
@@ -461,7 +464,10 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
         
     def add_end_caps(self):
         """ Add dummy cells or end caps around the array """
-        end_caps_enabled = cell_properties.bitcell.end_caps
+        try:
+            end_caps_enabled = cell_properties.bitcell.end_caps
+        except AttributeError:
+            end_caps_enabled = False
 
         # FIXME: These depend on the array size itself
         # Far top dummy row (first row above array is NOT flipped)
@@ -485,7 +491,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
         # Far left dummy col
         # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
         if not end_caps_enabled:
-            dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -len(self.left_rbl) - 1)
+            dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -self.rbl[0] - 1)  + self.unused_offset
         else:
             dummy_col_offset = self.bitcell_offset.scale(-(len(self.left_rbl)*(1+self.strap_offset.x/self.cell.width)) - (self.row_end_offset.x/self.cell.width), -len(self.left_rbl) - (self.col_end_offset.y/self.cell.height))
 
@@ -493,7 +499,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
         # Far right dummy col
         # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
         if not end_caps_enabled:
-            dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl)*(1+self.strap_offset.x/self.cell.width), -self.rbl[0] - 1) + self.bitcell_array_inst.lr()
+            dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl), -self.rbl[0] - 1) + self.bitcell_array_inst.lr()
         else:
             dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl)*(1+self.strap_offset.x/self.cell.width), -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.bitcell_array_inst.lr()
 

compiler/modules/replica_column.py

@@ -53,6 +53,8 @@ class replica_column(bitcell_base_array):
         self.create_instances()
 
     def create_layout(self):
+        self.height = self.total_size * self.cell.height
+        self.width = self.cell.width
 
         self.place_instances()
         self.add_layout_pins()
@@ -62,11 +64,15 @@ class replica_column(bitcell_base_array):
     def add_pins(self):
 
         self.create_all_bitline_names()
-        #remove 2 wordlines to account for top/bot
-        if not cell_properties.bitcell.end_caps:
+        try:
+            if cell_properties.bitcell.end_caps:
+                # remove 2 wordlines to account for top/bot
+                self.create_all_wordline_names(num_remove_wordlines=2)
+            else:
+                self.create_all_wordline_names()
+        except AttributeError:
             self.create_all_wordline_names()
-        else:
-            self.create_all_wordline_names(2)
+
         self.add_pin_list(self.all_bitline_names, "OUTPUT")
         self.add_pin_list(self.all_wordline_names, "INPUT")
 
@@ -112,7 +118,6 @@ class replica_column(bitcell_base_array):
             self.colenda_p_cent = factory.create(module_type="s8_col_end", version = "colenda_p_cent")
             self.add_mod(self.colenda_p_cent)
 
-
     def create_instances(self):
         self.cell_inst = {}
         if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
@@ -309,3 +314,5 @@ class replica_column(bitcell_base_array):
         for row, cell in self.cell_inst.items():
             if row != self.replica_bit:
                 self.graph_inst_exclude.add(cell)
+
+