mirror of https://github.com/VLSIDA/OpenRAM.git
Bus code converted to pins. Fix layers on control signal routes in bank.
This commit is contained in:
mrg
parent
0837432d45
commit
9cc36c6d3a
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@ -219,8 +219,6 @@ class layout():
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if not height:
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height = drc["minwidth_{}".format(layer)]
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lpp = techlayer[layer]
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if abs(offset[0]-5.16250)<0.01 and abs(offset[1]-8.70750)<0.01:
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import pdb; pdb.set_trace()
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self.objs.append(geometry.rectangle(lpp,
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offset,
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width,
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@ -838,51 +836,57 @@ class layout():
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if not pitch:
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pitch = getattr(self, "{}_pitch".format(layer))
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line_positions = {}
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pins = {}
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if vertical:
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for i in range(len(names)):
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line_offset = offset + vector(i * pitch,
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0)
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if make_pins:
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self.add_layout_pin(text=names[i],
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layer=layer,
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offset=line_offset,
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height=length)
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new_pin = self.add_layout_pin(text=names[i],
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layer=layer,
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offset=line_offset,
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height=length)
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else:
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self.add_rect(layer=layer,
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offset=line_offset,
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height=length)
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line_positions[names[i]] = line_offset + vector(half_minwidth, 0)
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rect = self.add_rect(layer=layer,
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offset=line_offset,
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height=length)
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new_pin = pin_layout(names[i],
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[rect.ll(), rect.ur()],
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layer)
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pins[names[i]] = new_pin
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else:
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for i in range(len(names)):
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line_offset = offset + vector(0,
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i * pitch + half_minwidth)
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if make_pins:
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self.add_layout_pin(text=names[i],
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layer=layer,
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offset=line_offset,
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width=length)
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new_pin = self.add_layout_pin(text=names[i],
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layer=layer,
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offset=line_offset,
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width=length)
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else:
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self.add_rect(layer=layer,
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offset=line_offset,
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width=length)
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# Make this the center of the rail
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line_positions[names[i]] = line_offset + vector(0.5 * length,
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half_minwidth)
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rect = self.add_rect(layer=layer,
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offset=line_offset,
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width=length)
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new_pin = pin_layout(names[i],
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[rect.ll(), rect.ur()],
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layer)
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pins[names[i]] = new_pin
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return line_positions
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return pins
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def connect_horizontal_bus(self, mapping, inst, bus_offsets,
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def connect_horizontal_bus(self, mapping, inst, bus_pins,
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layer_stack=("m1", "via1", "m2")):
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""" Horizontal version of connect_bus. """
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self.connect_bus(mapping, inst, bus_offsets, layer_stack, True)
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self.connect_bus(mapping, inst, bus_pins, layer_stack, True)
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def connect_vertical_bus(self, mapping, inst, bus_offsets,
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def connect_vertical_bus(self, mapping, inst, bus_pins,
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layer_stack=("m1", "via1", "m2")):
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""" Vertical version of connect_bus. """
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self.connect_bus(mapping, inst, bus_offsets, layer_stack, False)
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self.connect_bus(mapping, inst, bus_pins, layer_stack, False)
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def connect_bus(self, mapping, inst, bus_offsets, layer_stack, horizontal):
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def connect_bus(self, mapping, inst, bus_pins, layer_stack, horizontal):
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"""
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Connect a mapping of pin -> name for a bus. This could be
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replaced with a channel router in the future.
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@ -898,7 +902,7 @@ class layout():
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for (pin_name, bus_name) in mapping:
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pin = inst.get_pin(pin_name)
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pin_pos = pin.center()
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bus_pos = bus_offsets[bus_name]
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bus_pos = bus_pins[bus_name].center()
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if horizontal:
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# up/down then left/right
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@ -593,7 +593,7 @@ class bank(design.design):
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# Connect the inverter output to the central bus
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out_pos = self.bank_select_inst[port].get_pin(gated_bank_sel_signals[signal]).rc()
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name = self.control_signals[port][signal]
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bus_pos = vector(self.bus_xoffset[port][name].x, out_pos.y)
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bus_pos = vector(self.bus_pins[port][name].cx(), out_pos.y)
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self.add_path("m3", [out_pos, bus_pos])
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self.add_via_center(layers=self.m2_stack,
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offset=bus_pos)
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@ -628,19 +628,19 @@ class bank(design.design):
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# Overall central bus width. It includes all the column mux lines,
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# and control lines.
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self.bus_xoffset = [None] * len(self.all_ports)
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self.bus_pins = [None] * len(self.all_ports)
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# Port 0
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# The bank is at (0,0), so this is to the left of the y-axis.
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# 2 pitches on the right for vias/jogs to access the inputs
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control_bus_offset = vector(-self.m3_pitch * self.num_control_lines[0] - self.m3_pitch, self.min_y_offset)
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# The control bus is routed up to two pitches below the bitcell array
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control_bus_length = self.main_bitcell_array_bottom - self.min_y_offset - 2 * self.m1_pitch
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self.bus_xoffset[0] = self.create_bus(layer="m2",
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offset=control_bus_offset,
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names=self.control_signals[0],
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length=control_bus_length,
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vertical=True,
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make_pins=(self.num_banks==1))
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self.bus_pins[0] = self.create_bus(layer="m2",
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offset=control_bus_offset,
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names=self.control_signals[0],
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length=control_bus_length,
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vertical=True,
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make_pins=(self.num_banks==1))
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# Port 1
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if len(self.all_ports)==2:
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@ -649,12 +649,12 @@ class bank(design.design):
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control_bus_offset = vector(self.bitcell_array_right + self.m3_pitch,
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self.max_y_offset - control_bus_length)
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# The bus for the right port is reversed so that the rbl_wl is closest to the array
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self.bus_xoffset[1] = self.create_bus(layer="m2",
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offset=control_bus_offset,
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names=list(reversed(self.control_signals[1])),
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length=control_bus_length,
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vertical=True,
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make_pins=(self.num_banks==1))
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self.bus_pins[1] = self.create_bus(layer="m2",
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offset=control_bus_offset,
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names=list(reversed(self.control_signals[1])),
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length=control_bus_length,
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vertical=True,
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make_pins=(self.num_banks==1))
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def route_port_data_to_bitcell_array(self, port):
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""" Routing of BL and BR between port data and bitcell array """
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@ -919,39 +919,32 @@ class bank(design.design):
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# pre-decoder and this connection is in metal3
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connection = []
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connection.append((self.prefix + "p_en_bar{}".format(port),
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self.port_data_inst[port].get_pin("p_en_bar").lc(),
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self.port_data_inst[port].get_pin("p_en_bar").layer))
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self.port_data_inst[port].get_pin("p_en_bar")))
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rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port])
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connection.append((self.prefix + "wl_en{}".format(port),
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self.bitcell_array_inst.get_pin(rbl_wl_name).lc(),
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self.bitcell_array_inst.get_pin(rbl_wl_name).layer))
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self.bitcell_array_inst.get_pin(rbl_wl_name)))
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if port in self.write_ports:
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if port % 2:
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connection.append((self.prefix + "w_en{}".format(port),
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self.port_data_inst[port].get_pin("w_en").rc(),
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self.port_data_inst[port].get_pin("w_en").layer))
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else:
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connection.append((self.prefix + "w_en{}".format(port),
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self.port_data_inst[port].get_pin("w_en").lc(),
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self.port_data_inst[port].get_pin("w_en").layer))
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connection.append((self.prefix + "w_en{}".format(port),
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self.port_data_inst[port].get_pin("w_en")))
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if port in self.read_ports:
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connection.append((self.prefix + "s_en{}".format(port),
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self.port_data_inst[port].get_pin("s_en").lc(),
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self.port_data_inst[port].get_pin("s_en").layer))
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self.port_data_inst[port].get_pin("s_en")))
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for (control_signal, pin_pos, pin_layer) in connection:
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if port==0:
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y_offset = self.min_y_offset
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else:
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y_offset = self.max_y_offset
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control_pos = vector(self.bus_xoffset[port][control_signal].x, y_offset)
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if pin_layer == "m1":
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self.add_wire(self.m1_stack, [control_pos, pin_pos])
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elif pin_layer == "m3":
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self.add_wire(self.m2_stack[::-1], [control_pos, pin_pos])
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for (control_signal, pin) in connection:
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control_pin = self.bus_pins[port][control_signal]
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control_pos = vector(control_pin.cx(), pin.cy())
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# If the y doesn't overlap the bus, add a segment
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if pin.cy() < control_pin.by():
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self.add_path("m2", [control_pos, control_pin.bc()])
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elif pin.cy() > control_pin.uy():
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self.add_path("m2", [control_pos, control_pin.uc()])
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self.add_path(pin.layer, [control_pos, pin.center()])
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer="m2",
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offset=control_pos)
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# clk to wordline_driver
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control_signal = self.prefix + "wl_en{}".format(port)
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@ -961,7 +954,7 @@ class bank(design.design):
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else:
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pin_pos = self.port_address_inst[port].get_pin("wl_en").bc()
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mid_pos = pin_pos - vector(0, 2 * self.m2_gap) # to route down to the top of the bus
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control_x_offset = self.bus_xoffset[port][control_signal].x
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control_x_offset = self.bus_pins[port][control_signal].cx()
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control_pos = vector(control_x_offset, mid_pos.y)
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self.add_wire(self.m1_stack, [pin_pos, mid_pos, control_pos])
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self.add_via_center(layers=self.m1_stack,
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@ -384,10 +384,10 @@ class control_logic(design.design):
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height = self.control_logic_center.y - self.m2_pitch
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offset = vector(self.ctrl_dff_array.width, 0)
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self.rail_offsets = self.create_vertical_bus("m2",
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offset,
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self.internal_bus_list,
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height)
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self.input_bus = self.create_vertical_bus("m2",
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offset,
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self.internal_bus_list,
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height)
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def create_instances(self):
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""" Create all the instances """
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@ -493,7 +493,7 @@ class control_logic(design.design):
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# Connect to the rail level with the vdd rail
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# Use pen since it is in every type of control logic
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vdd_ypos = self.p_en_bar_nand_inst.get_pin("vdd").by()
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in_pos = vector(self.rail_offsets["rbl_bl_delay"].x, vdd_ypos)
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in_pos = vector(self.input_bus["rbl_bl_delay"].cx(), vdd_ypos)
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mid1 = vector(out_pos.x, in_pos.y)
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self.add_wire(self.m1_stack, [out_pos, mid1, in_pos])
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self.add_via_center(layers=self.m1_stack,
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@ -548,7 +548,7 @@ class control_logic(design.design):
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def route_gated_clk_bar(self):
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clkbuf_map = zip(["A"], ["clk_buf"])
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self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets)
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self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.input_bus)
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out_pos = self.clk_bar_inst.get_pin("Z").center()
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in_pos = self.gated_clk_bar_inst.get_pin("A").center()
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@ -558,7 +558,7 @@ class control_logic(design.design):
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clkbuf_map = zip(["B"], ["cs"])
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self.connect_vertical_bus(clkbuf_map,
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self.gated_clk_bar_inst,
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self.rail_offsets,
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self.input_bus,
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self.m2_stack[::-1])
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# The pin is on M1, so we need another via as well
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b_pin = self.gated_clk_bar_inst.get_pin("B")
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@ -586,12 +586,12 @@ class control_logic(design.design):
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clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"])
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self.connect_vertical_bus(clkbuf_map,
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self.gated_clk_buf_inst,
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self.rail_offsets)
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self.input_bus)
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clkbuf_map = zip(["Z"], ["gated_clk_buf"])
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self.connect_vertical_bus(clkbuf_map,
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self.gated_clk_buf_inst,
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self.rail_offsets,
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self.input_bus,
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self.m2_stack[::-1])
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# The pin is on M1, so we need another via as well
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z_pin = self.gated_clk_buf_inst.get_pin("Z")
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@ -614,7 +614,7 @@ class control_logic(design.design):
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def route_wlen(self):
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wlen_map = zip(["A"], ["gated_clk_bar"])
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self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets)
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self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.input_bus)
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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@ -639,7 +639,7 @@ class control_logic(design.design):
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def route_pen(self):
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in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"])
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self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.rail_offsets)
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self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.input_bus)
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out_pin = self.p_en_bar_nand_inst.get_pin("Z")
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out_pos = out_pin.center()
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@ -682,7 +682,7 @@ class control_logic(design.design):
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input_name = "cs"
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sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name])
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self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)
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self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.input_bus)
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self.connect_output(self.s_en_gate_inst, "Z", "s_en")
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@ -706,7 +706,7 @@ class control_logic(design.design):
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self.route_output_to_bus_jogged(self.rbl_bl_delay_inv_inst, "rbl_bl_delay_bar")
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rbl_map = zip(["A"], ["rbl_bl_delay"])
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self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets)
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self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.input_bus)
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def create_wen_row(self):
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@ -738,7 +738,7 @@ class control_logic(design.design):
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input_name = "cs"
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wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"])
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self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.rail_offsets)
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self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus)
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self.connect_output(self.w_en_gate_inst, "Z", "w_en")
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@ -761,13 +761,13 @@ class control_logic(design.design):
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dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"])
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else:
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dff_out_map = zip(["dout_bar_0"], ["cs"])
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self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, self.m2_stack[::-1])
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self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.input_bus, self.m2_stack[::-1])
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# Connect the clock rail to the other clock rail
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# by routing in the supply rail track to avoid channel conflicts
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in_pos = self.ctrl_dff_inst.get_pin("clk").uc()
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mid_pos = in_pos + vector(0, self.and2.height)
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rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y)
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rail_pos = vector(self.input_bus["clk_buf"].cx(), mid_pos.y)
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self.add_wire(self.m1_stack, [in_pos, mid_pos, rail_pos])
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self.add_via_center(layers=self.m1_stack,
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offset=rail_pos)
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@ -1001,8 +1001,8 @@ class control_logic(design.design):
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# Connect this at the bottom of the buffer
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out_pos = inst.get_pin("Z").center()
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mid1 = vector(out_pos.x, out_pos.y - 0.25 * inst.mod.height)
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mid2 = vector(self.rail_offsets[name].x, mid1.y)
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bus_pos = self.rail_offsets[name]
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mid2 = vector(self.input_bus[name].cx(), mid1.y)
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bus_pos = self.input_bus[name].center()
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self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos])
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# The pin is on M1, so we need another via as well
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self.add_via_center(layers=self.m1_stack,
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@ -209,7 +209,7 @@ class hierarchical_decoder(design.design):
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for i in range(2):
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index = pre_num * 2 + i
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input_pos = self.input_bus["addr_{}".format(index)]
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input_pos = self.input_bus["addr_{}".format(index)].center()
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in_name = "in_{}".format(i)
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decoder_pin = self.pre2x4_inst[pre_num].get_pin(in_name)
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@ -223,7 +223,7 @@ class hierarchical_decoder(design.design):
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for i in range(3):
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index = pre_num * 3 + i + self.no_of_pre2x4 * 2
|
||||
|
||||
input_pos = self.input_bus["addr_{}".format(index)]
|
||||
input_pos = self.input_bus["addr_{}".format(index)].center()
|
||||
|
||||
in_name = "in_{}".format(i)
|
||||
decoder_pin = self.pre3x8_inst[pre_num].get_pin(in_name)
|
||||
|
|
@ -572,7 +572,7 @@ class hierarchical_decoder(design.design):
|
|||
"""
|
||||
|
||||
pin_pos = pin.center()
|
||||
rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y)
|
||||
rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y)
|
||||
self.add_path(self.input_layer, [rail_pos, pin_pos])
|
||||
|
||||
self.add_via_stack_center(from_layer=self.bus_layer,
|
||||
|
|
@ -595,11 +595,11 @@ class hierarchical_decoder(design.design):
|
|||
pin_pos = pin.rc()
|
||||
mid_point1 = vector(x_offset, pin_pos.y)
|
||||
mid_point2 = vector(x_offset, y_offset)
|
||||
rail_pos = vector(self.predecode_bus[rail_name].x, mid_point2.y)
|
||||
rail_pos = vector(self.predecode_bus[rail_name].cx(), mid_point2.y)
|
||||
self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos])
|
||||
|
||||
# pin_pos = pin.center()
|
||||
# rail_pos = vector(self.predecode_bus[rail_name].x, pin_pos.y)
|
||||
# rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y)
|
||||
# self.add_path(self.output_layer, [pin_pos, rail_pos])
|
||||
self.add_via_stack_center(from_layer=pin.layer,
|
||||
to_layer=self.output_layer,
|
||||
|
|
|
|||
|
|
@ -202,15 +202,15 @@ class hierarchical_predecode(design.design):
|
|||
y_offset = pin.cy()
|
||||
in_pin = "in_{}".format(num)
|
||||
a_pin = "A_{}".format(num)
|
||||
in_pos = vector(self.input_rails[in_pin].x, y_offset)
|
||||
a_pos = vector(self.decode_rails[a_pin].x, y_offset)
|
||||
in_pos = vector(self.input_rails[in_pin].cx(), y_offset)
|
||||
a_pos = vector(self.decode_rails[a_pin].cx(), y_offset)
|
||||
self.add_path(self.input_layer, [in_pos, a_pos])
|
||||
self.add_via_stack_center(from_layer=self.input_layer,
|
||||
to_layer=self.bus_layer,
|
||||
offset=[self.input_rails[in_pin].x, y_offset])
|
||||
offset=[self.input_rails[in_pin].cx(), y_offset])
|
||||
self.add_via_stack_center(from_layer=self.input_layer,
|
||||
to_layer=self.bus_layer,
|
||||
offset=[self.decode_rails[a_pin].x, y_offset])
|
||||
offset=[self.decode_rails[a_pin].cx(), y_offset])
|
||||
|
||||
def route_output_and(self):
|
||||
"""
|
||||
|
|
@ -240,12 +240,12 @@ class hierarchical_predecode(design.design):
|
|||
# since this is where the p/n devices are and there are no
|
||||
# pins in the and gates.
|
||||
if OPTS.tech_name == "s8":
|
||||
rail_pos = vector(self.decode_rails[out_pin].x, inv_out_pos.y)
|
||||
rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y)
|
||||
self.add_path(self.output_layer, [inv_out_pos, rail_pos])
|
||||
else:
|
||||
y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch
|
||||
right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0)
|
||||
rail_pos = vector(self.decode_rails[out_pin].x, y_offset)
|
||||
rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset)
|
||||
self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
|
||||
|
||||
self.add_via_stack_center(from_layer=inv_out_pin.layer,
|
||||
|
|
@ -259,7 +259,7 @@ class hierarchical_predecode(design.design):
|
|||
# route input
|
||||
pin = self.inv_inst[inv_num].get_pin("A")
|
||||
inv_in_pos = pin.center()
|
||||
in_pos = vector(self.input_rails[in_pin].x, inv_in_pos.y)
|
||||
in_pos = vector(self.input_rails[in_pin].cx(), inv_in_pos.y)
|
||||
self.add_path(self.input_layer, [in_pos, inv_in_pos])
|
||||
self.add_via_stack_center(from_layer=pin.layer,
|
||||
to_layer=self.input_layer,
|
||||
|
|
@ -290,7 +290,7 @@ class hierarchical_predecode(design.design):
|
|||
for rail_pin, gate_pin in zip(index_lst, gate_lst):
|
||||
pin = self.and_inst[k].get_pin(gate_pin)
|
||||
pin_pos = pin.center()
|
||||
rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y)
|
||||
rail_pos = vector(self.decode_rails[rail_pin].cx(), pin_pos.y)
|
||||
self.add_path(self.input_layer, [rail_pos, pin_pos])
|
||||
self.add_via_stack_center(from_layer=self.input_layer,
|
||||
to_layer=self.bus_layer,
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ import debug
|
|||
from vector import vector
|
||||
from sram_factory import factory
|
||||
from globals import OPTS
|
||||
from tech import layer
|
||||
|
||||
|
||||
class precharge_array(design.design):
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ from tech import parameter
|
|||
from vector import vector
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
from tech import drc
|
||||
from tech import drc, layer
|
||||
|
||||
|
||||
class precharge(design.design):
|
||||
|
|
@ -38,10 +38,16 @@ class precharge(design.design):
|
|||
|
||||
if self.bitcell_bl_pin.layer == "m1":
|
||||
self.bitline_layer = "m1"
|
||||
self.en_layer = "m2"
|
||||
if "li" in layer:
|
||||
self.en_layer = "li"
|
||||
else:
|
||||
self.en_layer = "m2"
|
||||
else:
|
||||
self.bitline_layer = "m2"
|
||||
self.en_layer = "m1"
|
||||
if "li" in layer:
|
||||
self.en_layer = "li"
|
||||
else:
|
||||
self.en_layer = "m1"
|
||||
|
||||
# Creates the netlist and layout
|
||||
# Since it has variable height, it is not a pgate.
|
||||
|
|
|
|||
Loading…
Reference in New Issue