mirror of https://github.com/VLSIDA/OpenRAM.git
getattr for bank parameters
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@ -912,8 +912,8 @@ class bank(design.design):
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if not self.col_addr_size>0:
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return
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stack = layer_props.bank.stack
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pitch = layer_props.bank.pitch
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stack = getattr(self, layer_props.bank.stack)
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pitch = getattr(self, layer_props.bank.pitch)
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if self.col_addr_size == 1:
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