mirror of https://github.com/VLSIDA/OpenRAM.git
sense_amp: Allow custom pin names
we don't want to propagate the sense amp's bl/br names out of the sense_amp_array. Thus the sense_amp_array gets them named as "bl"/"br" again. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -120,7 +120,10 @@ class cell_properties():
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'bl' : 'bl',
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'br' : 'br',
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'en' : 'en'})
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self._sense_amp = _cell({'bl' : 'bl',
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'br' : 'br',
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'dout' : 'dout',
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'en' : 'en'})
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@property
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def bitcell(self):
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@ -141,3 +144,7 @@ class cell_properties():
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@property
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def write_driver(self):
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return self._write_driver
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@property
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def sense_amp(self):
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return self._sense_amp
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@ -9,6 +9,7 @@ import design
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import debug
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import utils
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from tech import GDS,layer, parameter,drc
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from tech import cell_properties as props
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from globals import OPTS
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import logical_effort
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@ -19,8 +20,12 @@ class sense_amp(design.design):
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the technology library.
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Sense amplifier to read a pair of bit-lines.
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"""
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pin_names = ["bl", "br", "dout", "en", "vdd", "gnd"]
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pin_names = [props.sense_amp.pin.bl,
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props.sense_amp.pin.br,
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props.sense_amp.pin.dout,
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props.sense_amp.pin.en,
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props.sense_amp.pin.vdd,
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props.sense_amp.pin.gnd]
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type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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if not OPTS.netlist_only:
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(width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
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@ -30,18 +35,18 @@ class sense_amp(design.design):
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pin_map = []
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def get_bl_names(self):
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return "bl"
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return props.sense_amp.pin.bl
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def get_br_names(self):
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return "br"
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return props.sense_amp.pin.br
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@property
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def dout_name(self):
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return "dout"
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return props.sense_amp.pin.dout
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@property
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def en_name(self):
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return "en"
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return props.sense_amp.pin.en
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def __init__(self, name):
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design.design.__init__(self, name)
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@ -34,11 +34,11 @@ class sense_amp_array(design.design):
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self.create_layout()
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def get_bl_name(self):
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bl_name = self.amp.get_bl_names()
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bl_name = "bl"
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return bl_name
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def get_br_name(self):
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br_name = self.amp.get_br_names()
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br_name = "br"
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return br_name
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@property
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