mirror of https://github.com/VLSIDA/OpenRAM.git
Route RBL to edge of bank.
This commit is contained in:
mrg
parent
05f9e809b4
commit
ee18f61cbf
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@ -126,11 +126,22 @@ class bank(design.design):
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bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
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bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name)
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self.add_layout_pin(text="rbl_bl{0}".format(port),
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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height=bl_pin.height(),
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width=bl_pin.width())
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# This will ensure the pin is only on the top or bottom edge
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if port % 2:
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via_offset = bl_pin.uc()
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left_right_offset = vector(self.max_x_offset, via_offset.y)
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else:
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via_offset = bl_pin.bc()
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left_right_offset = vector(self.min_x_offset, via_offset.y)
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if bl_pin == "m1":
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self.add_via_center(layers=self.m1_stack,
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offset=via_offset)
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self.add_via_center(layers=self.m2_stack,
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offset=via_offset)
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self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port),
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layer="m3",
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start=left_right_offset,
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end=via_offset)
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def route_bitlines(self, port):
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""" Route the bitlines depending on the port type rw, w, or r. """
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@ -662,9 +673,13 @@ class bank(design.design):
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inst2_bl_name = inst2.mod.get_bl_names() + "_{}"
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inst2_br_name = inst2.mod.get_br_names() + "_{}"
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self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols,
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inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name,
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inst2_bl_name=inst2_bl_name, inst2_br_name=inst2_br_name)
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self.connect_bitlines(inst1=inst1,
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inst2=inst2,
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num_bits=self.num_cols,
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inst1_bl_name=inst1_bl_name,
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inst1_br_name=inst1_br_name,
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inst2_bl_name=inst2_bl_name,
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inst2_br_name=inst2_br_name)
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# Connect the replica bitlines
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rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
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@ -310,8 +310,9 @@ class sram_1bank(sram_base):
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# Only input (besides pins) is the replica bitline
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src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
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dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
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self.connect_vbus_m2m3(src_pin, dest_pin)
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self.connect_hbus_m2m3(src_pin, dest_pin)
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def route_row_addr_dff(self):
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""" Connect the output of the row flops to the bank pins """
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for port in self.all_ports:
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@ -84,7 +84,7 @@ class sram_base(design, verilog, lef):
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def create_netlist(self):
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""" Netlist creation """
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start_time = datetime.now()
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start_time = datetime.datetime.now()
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# Must create the control logic before pins to get the pins
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self.add_modules()
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@ -96,20 +96,20 @@ class sram_base(design, verilog, lef):
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self.height=0
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if not OPTS.is_unit_test:
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print_time("Submodules", datetime.now(), start_time)
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print_time("Submodules", datetime.datetime.now(), start_time)
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def create_layout(self):
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""" Layout creation """
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start_time = datetime.now()
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start_time = datetime.datetime.now()
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self.place_instances()
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if not OPTS.is_unit_test:
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print_time("Placement", datetime.now(), start_time)
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print_time("Placement", datetime.datetime.now(), start_time)
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start_time = datetime.now()
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start_time = datetime.datetime.now()
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self.route_layout()
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self.route_supplies()
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if not OPTS.is_unit_test:
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print_time("Routing", datetime.now(), start_time)
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print_time("Routing", datetime.datetime.now(), start_time)
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self.add_lvs_correspondence_points()
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@ -119,11 +119,11 @@ class sram_base(design, verilog, lef):
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self.width = highest_coord[0]
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self.height = highest_coord[1]
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start_time = datetime.now()
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start_time = datetime.datetime.now()
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# We only enable final verification if we have routed the design
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self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True)
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if not OPTS.is_unit_test:
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print_time("Verification", datetime.now(), start_time)
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print_time("Verification", datetime.datetime.now(), start_time)
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def create_modules(self):
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debug.error("Must override pure virtual function.", -1)
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@ -526,6 +526,41 @@ class sram_base(design, verilog, lef):
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self.add_via_center(layers=self.m2_stack,
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offset=in_pos)
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def connect_hbus_m2m3(self, src_pin, dest_pin):
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"""
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Helper routine to connect an instance to a horizontal bus.
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Routes horizontal then vertical L shape.
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Dest pin is on M1/M2/M3.
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Src pin can be on M1/M2/M3.
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"""
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if src_pin.cx()<dest_pin.cx():
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in_pos = src_pin.rc()
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else:
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in_pos = src_pin.lc()
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if src_pin.cy() < dest_pin.cy():
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out_pos = dest_pin.lc()
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else:
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out_pos = dest_pin.rc()
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# move horizontal first
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self.add_wire(("m3", "via2", "m2"),
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[in_pos,
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vector(out_pos.x, in_pos.y),
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out_pos])
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if src_pin.layer=="m1":
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self.add_via_center(layers=self.m1_stack,
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offset=in_pos)
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if src_pin.layer in ["m1", "m2"]:
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self.add_via_center(layers=self.m2_stack,
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offset=in_pos)
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if dest_pin.layer=="m1":
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self.add_via_center(layers=self.m1_stack,
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offset=out_pos)
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if dest_pin.layer=="m3":
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self.add_via_center(layers=self.m2_stack,
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offset=out_pos)
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def sp_write(self, sp_name):
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# Write the entire spice of the object to the file
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############################################################
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