mirror of https://github.com/VLSIDA/OpenRAM.git
Must connect for replica cells other than top/bottom
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@ -188,6 +188,8 @@ class replica_column(design.design):
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for pin_name in ["vdd", "gnd"]:
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if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
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self.copy_power_pins(inst, pin_name)
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else:
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self.copy_layout_pin(inst, pin_name)
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def get_bitcell_pins(self, row, col):
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""" Creates a list of connections in the bitcell,
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