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Rework bitcells. 

Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
This commit is contained in:
mrg 2020-11-13 10:07:40 -08:00
parent 3567a3e913
commit c472a94f1e
50 changed files with 139 additions and 1052 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
compiler/base/custom_cell_properties.py
View File

@ -11,7 +11,7 @@ from globals import OPTS
class _pins:
def __init__(self, pin_dict):
# make the pins elements of the class to allow "." access.
# For example: props.bitcell.cell_6t.pin.bl = "foobar"
# For example: props.bitcell.cell_1port.pin.bl = "foobar"
for k, v in pin_dict.items():
self.__dict__[k] = v
@ -48,49 +48,36 @@ class _pgate:
class _bitcell:
def __init__(self, mirror, cell_6t, cell_1rw1r, cell_1w1r):
def __init__(self, mirror, cell_1port, cell_2port):
self.mirror = mirror
self._6t = cell_6t
self._1rw1r = cell_1rw1r
self._1w1r = cell_1w1r
self._1rw = cell_1port
self._2rw = cell_2port
def _default():
axis = _mirror_axis(True, False)
cell_6t = _cell({'bl': 'bl',
'br': 'br',
'wl': 'wl'})
cell_1port = _cell({'bl': 'bl',
'br': 'br',
'wl': 'wl'})
cell_1rw1r = _cell({'bl0': 'bl0',
cell_2port = _cell({'bl0': 'bl0',
'br0': 'br0',
'bl1': 'bl1',
'br1': 'br1',
'wl0': 'wl0',
'wl1': 'wl1'})
cell_1w1r = _cell({'bl0': 'bl0',
'br0': 'br0',
'bl1': 'bl1',
'br1': 'br1',
'wl0': 'wl0',
'wl1': 'wl1'})
return _bitcell(cell_6t=cell_6t,
cell_1rw1r=cell_1rw1r,
cell_1w1r=cell_1w1r,
return _bitcell(cell_1port=cell_1port,
cell_2port=cell_2port,
mirror=axis)
@property
def cell_6t(self):
return self._6t
def cell_1port(self):
return self._1rw
@property
def cell_1rw1r(self):
return self._1rw1r
@property
def cell_1w1r(self):
return self._1w1r
def cell_2port(self):
return self._2rw
class _dff:
@ -127,22 +114,18 @@ class cell_properties():
"""
def __init__(self):
self.names = {}
self.names["bitcell"] = "cell_6t"
self.names["bitcell_1rw_1r"] = "cell_1rw_1r"
self.names["bitcell_1w_1r"] = "cell_1w_1r"
self.names["dummy_bitcell"] = "dummy_cell_6t"
self.names["dummy_bitcell_1rw_1r"] = "dummy_cell_1rw_1r"
self.names["dummy_bitcell_1w_1r"] = "dummy_cell_1w_1r"
self.names["replica_bitcell"] = "replica_cell_6t"
self.names["replica_bitcell_1rw_1r"] = "replica_cell_1rw_1r"
self.names["replica_bitcell_1w_1r"] = "replica_cell_1w_1r"
self.names["col_cap_bitcell_6t"] = "col_cap_cell_6t"
self.names["col_cap_bitcell_1rw_1r"] = "col_cap_cell_1rw_1r"
self.names["col_cap_bitcell_1w_1r"] = "col_cap_cell_1w_1r"
self.names["row_cap_bitcell_6t"] = "row_cap_cell_6t"
self.names["row_cap_bitcell_1rw_1r"] = "row_cap_cell_1rw_1r"
self.names["row_cap_bitcell_1w_1r"] = "row_cap_cell_1w_1r"
self.names["bitcell_1port"] = "cell_1rw"
self.names["bitcell_2port"] = "cell_2rw"
self.names["dummy_bitcell_1port"] = "dummy_cell_1rw"
self.names["dummy_bitcell_2port"] = "dummy_cell_2rw"
self.names["replica_bitcell_1port"] = "replica_cell_1rw"
self.names["replica_bitcell_2port"] = "replica_cell_2rw"
self.names["col_cap_bitcell_1port"] = "col_cap_cell_1rw"
self.names["col_cap_bitcell_2port"] = "col_cap_cell_2rw"
self.names["row_cap_bitcell_1port"] = "row_cap_cell_1rw"
self.names["row_cap_bitcell_2port"] = "row_cap_cell_2rw"
self._bitcell = _bitcell._default()
self._ptx = _ptx(model_is_subckt=False,

2
compiler/base/hierarchy_spice.py
View File

@ -104,7 +104,7 @@ class spice():
debug.error("{} spice subcircuit port names do not match pin_names\
\n SPICE names={}\
\n Module names={}\
".format(self.name, self.pin, self.pin_names), 1)
".format(self.name, self.pins, self.pin_names), 1)
self.pin_type = {pin: type for pin, type in zip(self.pin_names, type_list)}
def get_pin_type(self, name):

24
compiler/bitcells/bitcell_1port.py
View File

@ -18,11 +18,11 @@ class bitcell_1port(bitcell_base.bitcell_base):
library.
"""
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
pin_names = [props.bitcell.cell_1port.pin.bl,
props.bitcell.cell_1port.pin.br,
props.bitcell.cell_1port.pin.wl,
props.bitcell.cell_1port.pin.vdd,
props.bitcell.cell_1port.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
@ -34,37 +34,37 @@ class bitcell_1port(bitcell_base.bitcell_base):
def get_all_wl_names(self):
""" Creates a list of all wordline pin names """
row_pins = [props.bitcell.cell_6t.pin.wl]
row_pins = [props.bitcell.cell_1port.pin.wl]
return row_pins
def get_all_bitline_names(self):
""" Creates a list of all bitline pin names (both bl and br) """
pin = props.bitcell.cell_6t.pin
pin = props.bitcell.cell_1port.pin
column_pins = [pin.bl, pin.br]
return column_pins
def get_all_bl_names(self):
""" Creates a list of all bl pins names """
return [props.bitcell.cell_6t.pin.bl]
return [props.bitcell.cell_1port.pin.bl]
def get_all_br_names(self):
""" Creates a list of all br pins names """
return [props.bitcell.cell_6t.pin.br]
return [props.bitcell.cell_1port.pin.br]
def get_bl_name(self, port=0):
"""Get bl name"""
debug.check(port == 0, "One port for bitcell only.")
return props.bitcell.cell_6t.pin.bl
return props.bitcell.cell_1port.pin.bl
def get_br_name(self, port=0):
"""Get bl name"""
debug.check(port == 0, "One port for bitcell only.")
return props.bitcell.cell_6t.pin.br
return props.bitcell.cell_1port.pin.br
def get_wl_name(self, port=0):
"""Get wl name"""
debug.check(port == 0, "One port for bitcell only.")
return props.bitcell.cell_6t.pin.wl
return props.bitcell.cell_1port.pin.wl
def build_graph(self, graph, inst_name, port_nets):
"""

54
compiler/bitcells/bitcell_2port.py
View File

@ -18,21 +18,21 @@ class bitcell_2port(bitcell_base.bitcell_base):
library.
"""
pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
props.bitcell.cell_1rw1r.pin.br0,
props.bitcell.cell_1rw1r.pin.bl1,
props.bitcell.cell_1rw1r.pin.br1,
props.bitcell.cell_1rw1r.pin.wl0,
props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.vdd,
props.bitcell.cell_1rw1r.pin.gnd]
pin_names = [props.bitcell.cell_2port.pin.bl0,
props.bitcell.cell_2port.pin.br0,
props.bitcell.cell_2port.pin.bl1,
props.bitcell.cell_2port.pin.br1,
props.bitcell.cell_2port.pin.wl0,
props.bitcell.cell_2port.pin.wl1,
props.bitcell.cell_2port.pin.vdd,
props.bitcell.cell_2port.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"INPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create bitcell with 1RW and 1R Port")
debug.info(2, "Create bitcell with 2 ports")
self.nets_match = self.do_nets_exist(self.storage_nets)
@ -46,7 +46,7 @@ class bitcell_2port(bitcell_base.bitcell_base):
Creates a list of connections in the bitcell,
indexed by column and row, for instance use in bitcell_array
"""
pin_name = props.bitcell.cell_1rw1r.pin
pin_name = props.bitcell.cell_2port.pin
bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
"{0}_{1}".format(pin_name.br0, col),
"{0}_{1}".format(pin_name.bl1, col),
@ -59,43 +59,43 @@ class bitcell_2port(bitcell_base.bitcell_base):
def get_all_wl_names(self):
""" Creates a list of all wordline pin names """
return [props.bitcell.cell_1rw1r.pin.wl0,
props.bitcell.cell_1rw1r.pin.wl1]
return [props.bitcell.cell_2port.pin.wl0,
props.bitcell.cell_2port.pin.wl1]
def get_all_bitline_names(self):
""" Creates a list of all bitline pin names (both bl and br) """
return [props.bitcell.cell_1rw1r.pin.bl0,
props.bitcell.cell_1rw1r.pin.br0,
props.bitcell.cell_1rw1r.pin.bl1,
props.bitcell.cell_1rw1r.pin.br1]
return [props.bitcell.cell_2port.pin.bl0,
props.bitcell.cell_2port.pin.br0,
props.bitcell.cell_2port.pin.bl1,
props.bitcell.cell_2port.pin.br1]
def get_all_bl_names(self):
""" Creates a list of all bl pins names """
return [props.bitcell.cell_1rw1r.pin.bl0,
props.bitcell.cell_1rw1r.pin.bl1]
return [props.bitcell.cell_2port.pin.bl0,
props.bitcell.cell_2port.pin.bl1]
def get_all_br_names(self):
""" Creates a list of all br pins names """
return [props.bitcell.cell_1rw1r.pin.br0,
props.bitcell.cell_1rw1r.pin.br1]
return [props.bitcell.cell_2port.pin.br0,
props.bitcell.cell_2port.pin.br1]
def get_read_bl_names(self):
""" Creates a list of bl pin names associated with read ports """
return [props.bitcell.cell_1rw1r.pin.bl0,
props.bitcell.cell_1rw1r.pin.bl1]
return [props.bitcell.cell_2port.pin.bl0,
props.bitcell.cell_2port.pin.bl1]
def get_read_br_names(self):
""" Creates a list of br pin names associated with read ports """
return [props.bitcell.cell_1rw1r.pin.br0,
props.bitcell.cell_1rw1r.pin.br1]
return [props.bitcell.cell_2port.pin.br0,
props.bitcell.cell_2port.pin.br1]
def get_write_bl_names(self):
""" Creates a list of bl pin names associated with write ports """
return [props.bitcell.cell_1rw1r.pin.bl0]
return [props.bitcell.cell_2port.pin.bl0]
def get_write_br_names(self):
""" Creates a list of br pin names asscociated with write ports"""
return [props.bitcell.cell_1rw1r.pin.br1]
return [props.bitcell.cell_2port.pin.br1]
def get_bl_name(self, port=0):
"""Get bl name by port"""
@ -118,7 +118,7 @@ class bitcell_2port(bitcell_base.bitcell_base):
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
# Edges hardcoded here. Essentially wl->bl/br for both ports.
# Port 0 edges
pins = props.bitcell.cell_1rw1r.pin
pins = props.bitcell.cell_2port.pin
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
# Port 1 edges

12
compiler/bitcells/dummy_bitcell_1port.py
View File

@ -10,18 +10,18 @@ from tech import cell_properties as props
import bitcell_base
class dummy_bitcell(bitcell_base.bitcell_base):
class dummy_bitcell_1port(bitcell_base.bitcell_base):
"""
A single bit cell (6T, 8T, etc.) This module implements the
single memory cell used in the design. It is a hand-made cell, so
the layout and netlist should be available in the technology
library.
"""
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
pin_names = [props.bitcell.cell_1port.pin.bl,
props.bitcell.cell_1port.pin.br,
props.bitcell.cell_1port.pin.wl,
props.bitcell.cell_1port.pin.vdd,
props.bitcell.cell_1port.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name):

30
compiler/bitcells/dummy_bitcell_2port.py
View File

@ -10,22 +10,26 @@ from tech import cell_properties as props
import bitcell_base
class dummy_bitcell(bitcell_base.bitcell_base):
class dummy_bitcell_2port(bitcell_base.bitcell_base):
"""
A single bit cell (6T, 8T, etc.) This module implements the
single memory cell used in the design. It is a hand-made cell, so
the layout and netlist should be available in the technology
library.
"""
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
A single bit cell which is forced to store a 0.
This module implements the single memory cell used in the design. It
is a hand-made cell, so the layout and netlist should be available in
the technology library. """
pin_names = [props.bitcell.cell_2port.pin.bl0,
props.bitcell.cell_2port.pin.br0,
props.bitcell.cell_2port.pin.bl1,
props.bitcell.cell_2port.pin.br1,
props.bitcell.cell_2port.pin.wl0,
props.bitcell.cell_2port.pin.wl1,
props.bitcell.cell_2port.pin.vdd,
props.bitcell.cell_2port.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"INPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create dummy bitcell")
debug.info(2, "Create dummy bitcell 2 port object")

12
compiler/bitcells/replica_bitcell_1port.py
View File

@ -12,18 +12,18 @@ from tech import parameter, drc
import logical_effort
class replica_bitcell(bitcell_base.bitcell_base):
class replica_bitcell_1port(bitcell_base.bitcell_base):
"""
A single bit cell (6T, 8T, etc.)
This module implements the single memory cell used in the design. It
is a hand-made cell, so the layout and netlist should be available in
the technology library. """
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
pin_names = [props.bitcell.cell_1port.pin.bl,
props.bitcell.cell_1port.pin.br,
props.bitcell.cell_1port.pin.wl,
props.bitcell.cell_1port.pin.vdd,
props.bitcell.cell_1port.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name):

43
compiler/bitcells/replica_bitcell_2port.py
View File

@ -12,23 +12,26 @@ from tech import parameter, drc
import logical_effort
class replica_bitcell(bitcell_base.bitcell_base):
class replica_bitcell_2port(bitcell_base.bitcell_base):
"""
A single bit cell (6T, 8T, etc.)
A single bit cell which is forced to store a 0.
This module implements the single memory cell used in the design. It
is a hand-made cell, so the layout and netlist should be available in
the technology library. """
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
pin_names = [props.bitcell.cell_2port.pin.bl0,
props.bitcell.cell_2port.pin.br0,
props.bitcell.cell_2port.pin.bl1,
props.bitcell.cell_2port.pin.br1,
props.bitcell.cell_2port.pin.wl0,
props.bitcell.cell_2port.pin.wl1,
props.bitcell.cell_2port.pin.vdd,
props.bitcell.cell_2port.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create replica bitcell object")
debug.info(2, "Create replica bitcell 2 port object")
def get_stage_effort(self, load):
parasitic_delay = 1
@ -41,17 +44,19 @@ class replica_bitcell(bitcell_base.bitcell_base):
"""Return the relative capacitance of the access transistor gates"""
# FIXME: This applies to bitline capacitances as well.
# FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
access_tx_cin = parameter["6T_access_size"] / drc["minwidth_tx"]
return 2 * access_tx_cin
def analytical_power(self, corner, load):
"""Bitcell power in nW. Only characterizes leakage."""
from tech import spice
leakage = spice["bitcell_leakage"]
dynamic = 0 # FIXME
total_power = self.return_power(dynamic, leakage)
return total_power
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges based on inputs/outputs. Overrides base class function."""
self.add_graph_edges(graph, port_nets)
"""Adds edges to graph. Multiport bitcell timing graph is too complex
to use the add_graph_edges function."""
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
pins = props.bitcell.cell_2port.pin
# Edges hardcoded here. Essentially wl->bl/br for both ports.
# Port 0 edges
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
# Port 1 edges
graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)

10
compiler/globals.py
View File

@ -213,15 +213,15 @@ def setup_bitcell():
# If we have non-1rw ports,
# and the user didn't over-ride the bitcell manually,
# figure out the right bitcell to use
if OPTS.bitcell == "bitcell":
if OPTS.bitcell == "pbitcell":
OPTS.bitcell = "pbitcell"
OPTS.dummy_bitcell = "dummy_pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
else:
num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
OPTS.bitcell = "bitcell_{}port".format(num_ports)
OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell
OPTS.replica_bitcell = "replica_" + OPTS.bitcell
elif OPTS.bitcell == "pbitcell":
OPTS.bitcell = "pbitcell"
OPTS.dummy_bitcell = "dummy_pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
# See if bitcell exists
try:

2
compiler/modules/bitcell_array.py
View File

@ -62,7 +62,7 @@ class bitcell_array(bitcell_base_array):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.cell)
mod=self.cell)
self.connect_inst(self.get_bitcell_pins(row, col))
def analytical_power(self, corner, load):

3
compiler/options.py
View File

@ -148,10 +148,9 @@ class options(optparse.Values):
# These are the default modules that can be over-riden
bitcell_suffix = ""
bank_select = "bank_select"
bitcell_array = "bitcell_array"
bitcell = "bitcell_1port"
bitcell = "bitcell"
buf_dec = "pbuf"
column_mux_array = "column_mux_array"
control_logic = "control_logic"

BIN
technology/freepdk45/gds_lib/cell_6t.gds → technology/freepdk45/gds_lib/cell_1rw.gds
View File

Binary file not shown.

BIN
technology/freepdk45/gds_lib/dummy_cell_6t.gds → technology/freepdk45/gds_lib/dummy_cell_1rw.gds
View File

Binary file not shown.

BIN
technology/freepdk45/gds_lib/replica_cell_6t.gds → technology/freepdk45/gds_lib/replica_cell_1rw.gds
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Binary file not shown.

4
technology/freepdk45/sp_lib/cell_6t.sp → technology/freepdk45/sp_lib/cell_1rw.sp vendored
View File

@ -1,5 +1,5 @@
.SUBCKT cell_6t bl br wl vdd gnd
.SUBCKT cell_1rw bl br wl vdd gnd
* Inverter 1
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n
@ -11,5 +11,5 @@ MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
* Access transistors
MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
MM2 br wl Q_bar gnd NMOS_VTG W=135.00n L=50n
.ENDS cell_6t
.ENDS cell_1rw

4
technology/freepdk45/sp_lib/dummy_cell_6t.sp → technology/freepdk45/sp_lib/dummy_cell_1rw.sp vendored
View File

@ -1,5 +1,5 @@
.SUBCKT dummy_cell_6t bl br wl vdd gnd
.SUBCKT dummy_cell_1rw bl br wl vdd gnd
* Inverter 1
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n
@ -11,5 +11,5 @@ MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n
* Access transistors
MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n
MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n
.ENDS cell_6t
.ENDS cell_1rw

4
technology/freepdk45/sp_lib/replica_cell_6t.sp → technology/freepdk45/sp_lib/replica_cell_1rw.sp vendored
View File

@ -1,5 +1,5 @@
.SUBCKT replica_cell_6t bl br wl vdd gnd
.SUBCKT replica_cell_1rw bl br wl vdd gnd
* Inverter 1
MM0 vdd Q gnd gnd NMOS_VTG W=205.00n L=50n
MM4 vdd Q vdd vdd PMOS_VTG W=90n L=50n
@ -11,5 +11,5 @@ MM5 Q vdd vdd vdd PMOS_VTG W=90n L=50n
* Access transistors
MM3 bl wl Q gnd NMOS_VTG W=135.00n L=50n
MM2 br wl vdd gnd NMOS_VTG W=135.00n L=50n
.ENDS cell_6t
.ENDS cell_1rw

6
technology/freepdk45/tech/tech.py
View File

@ -35,12 +35,6 @@ cell_properties.bitcell.mirror.x = True
cell_properties.bitcell.mirror.y = False
cell_properties.bitcell_power_pin_directions = ("V", "V")
cell_properties.names["bitcell_1port"] = "cell_6t"
cell_properties.names["dummy_bitcell_1port"] = "dummy_cell_6t"
cell_properties.names["replcia_bitcell_1port"] = "replica_cell_6t"
cell_properties.names["bitcell_2port"] = "cell_2rw"
cell_properties.names["dummy_bitcell_2port"] = "dummy_cell_2rw"
cell_properties.names["replica_bitcell_2port"] = "replica_cell_2rw"
###################################################
# Custom cell properties

BIN
technology/scn4m_subm/gds_lib/cell_1rw.gds Normal file
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BIN
technology/scn4m_subm/gds_lib/cell_6t.gds
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BIN
technology/scn4m_subm/gds_lib/dummy_cell_1rw.gds Normal file
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BIN
technology/scn4m_subm/gds_lib/dummy_cell_6t.gds
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BIN
technology/scn4m_subm/gds_lib/replica_cell_1rw.gds Normal file
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BIN
technology/scn4m_subm/gds_lib/replica_cell_6t.gds
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0
technology/scn4m_subm/mag_lib/cell_6t.mag → technology/scn4m_subm/mag_lib/cell_1rw.mag
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146
technology/scn4m_subm/mag_lib/cell_1w_1r.mag
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@ -1,146 +0,0 @@
magic
tech scmos
timestamp 1577067400
<< nwell >>
rect 0 46 54 75
<< pwell >>
rect 0 0 54 46
<< ntransistor >>
rect 14 33 16 37
rect 22 29 24 37
rect 30 29 32 37
rect 38 33 40 37
rect 14 17 16 23
rect 22 17 24 23
rect 30 17 32 23
rect 38 17 40 23
<< ptransistor >>
rect 22 54 24 57
rect 30 54 32 57
<< ndiffusion >>
rect 13 33 14 37
rect 16 33 17 37
rect 21 33 22 37
rect 17 29 22 33
rect 24 29 25 37
rect 29 29 30 37
rect 32 33 33 37
rect 37 33 38 37
rect 40 33 41 37
rect 32 29 37 33
rect 9 21 14 23
rect 13 17 14 21
rect 16 17 22 23
rect 24 17 25 23
rect 29 17 30 23
rect 32 17 38 23
rect 40 21 45 23
rect 40 17 41 21
<< pdiffusion >>
rect 21 54 22 57
rect 24 54 25 57
rect 29 54 30 57
rect 32 54 33 57
<< ndcontact >>
rect 9 33 13 37
rect 17 33 21 37
rect 25 29 29 37
rect 33 33 37 37
rect 41 33 45 37
rect 9 17 13 21
rect 25 17 29 23
rect 41 17 45 21
<< pdcontact >>
rect 17 54 21 58
rect 25 54 29 58
rect 33 54 37 58
<< psubstratepcontact >>
rect 25 9 29 13
<< nsubstratencontact >>
rect 25 68 29 72
<< polysilicon >>
rect 22 57 24 60
rect 30 57 32 60
rect 22 44 24 54
rect 30 51 32 54
rect 31 47 32 51
rect 14 37 16 44
rect 22 40 23 44
rect 22 37 24 40
rect 30 37 32 47
rect 38 37 40 44
rect 14 31 16 33
rect 38 31 40 33
rect 14 23 16 24
rect 22 23 24 29
rect 30 23 32 29
rect 38 23 40 24
rect 14 15 16 17
rect 22 15 24 17
rect 30 15 32 17
rect 38 15 40 17
<< polycontact >>
rect 27 47 31 51
rect 10 40 14 44
rect 23 40 27 44
rect 40 40 44 44
rect 12 24 16 28
rect 38 24 42 28
<< metal1 >>
rect 0 68 25 72
rect 29 68 54 72
rect 0 61 54 65
rect 10 44 14 61
rect 17 51 20 54
rect 17 47 27 51
rect 17 37 20 47
rect 34 44 37 54
rect 27 40 37 44
rect 40 44 44 61
rect 34 37 37 40
rect 6 33 9 37
rect 45 33 48 37
rect 25 23 29 29
rect 25 13 29 17
rect 0 9 25 13
rect 29 9 54 13
rect 0 2 16 6
rect 20 2 34 6
rect 38 2 54 6
<< m2contact >>
rect 25 68 29 72
rect 25 54 29 58
rect 2 33 6 37
rect 48 33 52 37
rect 16 24 20 28
rect 34 24 38 28
rect 9 17 13 21
rect 41 17 45 21
rect 16 2 20 6
rect 34 2 38 6
<< metal2 >>
rect 2 37 6 72
rect 2 0 6 33
rect 9 21 13 72
rect 25 58 29 68
rect 9 0 13 17
rect 16 6 20 24
rect 34 6 38 24
rect 41 21 45 72
rect 41 0 45 17
rect 48 37 52 72
rect 48 0 52 33
<< comment >>
rect 0 0 54 70
<< labels >>
rlabel metal1 19 63 19 63 1 wl0
rlabel metal1 19 70 19 70 5 vdd
rlabel metal1 27 4 27 4 1 wl1
rlabel psubstratepcontact 27 11 27 11 1 gnd
rlabel metal2 4 7 4 7 2 bl0
rlabel metal2 11 7 11 7 1 bl1
rlabel metal2 43 7 43 7 1 br1
rlabel metal2 50 7 50 7 8 br0
rlabel polycontact 29 49 29 49 1 Q
rlabel polycontact 25 42 25 42 1 Q_bar
<< end >>

0
technology/scn4m_subm/mag_lib/cell_1rw_1r.mag → technology/scn4m_subm/mag_lib/cell_2rw.mag
View File

41
technology/scn4m_subm/mag_lib/cell_6t.ext
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@ -1,41 +0,0 @@
timestamp 1536091415
version 8.2
tech scmos
style TSMC0.35um(tsmc35)from:t11c
scale 1000 1 5
resistclasses 3700 2800 1018000 1018000 1 6000 6000 80 70 80 40
node "comment_0_0#" 0 0 0 0 bb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "br" 6 -1.43219e-14 96 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3456 464 0 0 0 0
node "bl" 6 -8.88178e-16 40 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3200 432 0 0 0 0
node "wl" 115 -2.89546e-13 -8 12 p 0 0 0 0 0 0 0 0 0 0 1536 360 0 0 2496 344 0 0 0 0 0 0
node "a_36_40#" 140 -3.51719e-13 36 40 ndif 960 144 304 72 0 0 0 0 0 0 1984 424 0 0 2048 288 0 0 0 0 0 0
node "a_28_32#" 160 -8.06466e-13 28 32 p 960 144 304 72 0 0 0 0 0 0 2000 456 0 0 1920 272 0 0 0 0 0 0
node "gnd" 41 -27.888 -32 -32 pw 1792 240 512 128 0 0 0 0 29600 696 0 0 0 0 2688 400 6400 864 0 0 0 0
equiv "gnd" "gnd"
node "vdd" 2340 2596 -32 116 nw 256 64 800 176 17600 576 0 0 0 0 0 0 0 0 3456 464 256 64 0 0 0 0
cap "wl" "bl" 189.768
cap "a_36_40#" "br" 17.59
cap "wl" "br" 189.768
cap "vdd" "bl" 135.015
cap "bl" "br" 27.492
cap "vdd" "br" 117.084
cap "gnd" "a_28_32#" 880.405
cap "gnd" "a_36_40#" 401.284
cap "a_28_32#" "a_36_40#" 272.793
cap "gnd" "wl" 1198.41
cap "gnd" "bl" 712.11
cap "a_28_32#" "wl" 108.364
cap "vdd" "gnd" 510.12
cap "gnd" "br" 698.471
cap "a_36_40#" "wl" 108.364
cap "a_28_32#" "bl" 104.205
cap "vdd" "a_28_32#" 430.812
cap "a_36_40#" "bl" 29.396
cap "a_28_32#" "br" 308.488
cap "vdd" "a_36_40#" 709.108
fet nfet 96 12 97 13 128 48 "gnd" "wl" 16 0 "br" 16 0 "a_28_32#" 16 0
fet nfet 40 12 41 13 128 48 "gnd" "wl" 16 0 "bl" 16 0 "a_36_40#" 16 0
fet nfet 116 40 117 41 256 80 "gnd" "a_36_40#" 16 0 "a_28_32#" 32 0 "gnd" 32 0
fet nfet 28 40 29 41 256 80 "gnd" "a_28_32#" 16 0 "gnd" 32 0 "a_36_40#" 32 0
fet pfet 108 148 109 149 192 56 "vdd" "a_36_40#" 32 0 "a_28_32#" 12 0 "vdd" 12 0
fet pfet 28 148 29 149 192 56 "vdd" "a_28_32#" 32 0 "vdd" 12 0 "a_36_40#" 12 0

15
technology/scn4m_subm/mag_lib/cell_6t.spice
View File

@ -1,15 +0,0 @@
* SPICE3 file created from cell_6t.ext - technology: scmos
M1000 a_36_40# a_28_32# vdd vdd pfet w=0.6u l=0.8u
+ ad=0.76p pd=3.6u as=2p ps=8.8u
M1001 vdd a_36_40# a_28_32# vdd pfet w=0.6u l=0.8u
+ ad=0p pd=0u as=0.76p ps=3.6u
M1002 a_36_40# a_28_32# gnd gnd nfet w=1.6u l=0.4u
+ ad=2.4p pd=7.2u as=4.48p ps=12u
M1003 gnd a_36_40# a_28_32# gnd nfet w=1.6u l=0.4u
+ ad=0p pd=0u as=2.4p ps=7.2u
M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
+ ad=0p pd=0u as=0.8p ps=3.6u
M1005 a_28_32# wl br gnd nfet w=0.8u l=0.4u
+ ad=0p pd=0u as=0.8p ps=3.6u
C0 vdd 0 2.60fF

0
technology/scn4m_subm/mag_lib/dummy_cell_6t.mag → technology/scn4m_subm/mag_lib/dummy_cell_1rw.mag
View File

138
technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag
View File

@ -1,138 +0,0 @@
magic
tech scmos
timestamp 1577067400
<< nwell >>
rect 0 46 54 75
<< pwell >>
rect 0 0 54 46
<< ntransistor >>
rect 14 33 16 37
rect 22 29 24 37
rect 30 29 32 37
rect 38 33 40 37
rect 14 17 16 23
rect 22 17 24 23
rect 30 17 32 23
rect 38 17 40 23
<< ptransistor >>
rect 22 54 24 57
rect 30 54 32 57
<< ndiffusion >>
rect 13 33 14 37
rect 16 33 17 37
rect 21 33 22 37
rect 17 29 22 33
rect 24 29 25 37
rect 29 29 30 37
rect 32 33 33 37
rect 37 33 38 37
rect 40 33 41 37
rect 32 29 37 33
rect 9 21 14 23
rect 13 17 14 21
rect 16 17 22 23
rect 24 17 25 23
rect 29 17 30 23
rect 32 17 38 23
rect 40 21 45 23
rect 40 17 41 21
<< pdiffusion >>
rect 21 54 22 57
rect 24 54 25 57
rect 29 54 30 57
rect 32 54 33 57
<< ndcontact >>
rect 9 33 13 37
rect 17 33 21 37
rect 25 29 29 37
rect 33 33 37 37
rect 41 33 45 37
rect 9 17 13 21
rect 25 17 29 23
rect 41 17 45 21
<< pdcontact >>
rect 17 54 21 58
rect 25 54 29 58
rect 33 54 37 58
<< psubstratepcontact >>
rect 25 9 29 13
<< nsubstratencontact >>
rect 25 68 29 72
<< polysilicon >>
rect 22 57 24 60
rect 30 57 32 60
rect 22 44 24 54
rect 30 51 32 54
rect 31 47 32 51
rect 14 37 16 44
rect 22 40 23 44
rect 22 37 24 40
rect 30 37 32 47
rect 38 37 40 44
rect 14 31 16 33
rect 38 31 40 33
rect 14 23 16 24
rect 22 23 24 29
rect 30 23 32 29
rect 38 23 40 24
rect 14 15 16 17
rect 22 15 24 17
rect 30 15 32 17
rect 38 15 40 17
<< polycontact >>
rect 27 47 31 51
rect 10 40 14 44
rect 23 40 27 44
rect 40 40 44 44
rect 12 24 16 28
rect 38 24 42 28
<< metal1 >>
rect 0 68 25 72
rect 29 68 54 72
rect 0 61 54 65
rect 10 44 14 61
rect 17 51 20 54
rect 17 47 27 51
rect 17 37 20 47
rect 34 44 37 54
rect 27 40 37 44
rect 40 44 44 61
rect 34 37 37 40
rect 2 33 9 37
rect 45 33 52 37
rect 25 23 29 29
rect 25 13 29 17
rect 0 9 25 13
rect 29 9 54 13
rect 0 2 16 6
rect 20 2 34 6
rect 38 2 54 6
<< m2contact >>
rect 25 68 29 72
rect 25 54 29 58
rect 16 24 20 28
rect 34 24 38 28
rect 16 2 20 6
rect 34 2 38 6
<< metal2 >>
rect 2 0 6 72
rect 9 0 13 72
rect 25 58 29 68
rect 16 6 20 24
rect 34 6 38 24
rect 41 0 45 72
rect 48 0 52 72
<< comment >>
rect 0 0 54 70
<< labels >>
rlabel metal1 19 63 19 63 1 wl0
rlabel metal1 19 70 19 70 5 vdd
rlabel metal1 27 4 27 4 1 wl1
rlabel psubstratepcontact 27 11 27 11 1 gnd
rlabel metal2 4 7 4 7 2 bl0
rlabel metal2 11 7 11 7 1 bl1
rlabel metal2 43 7 43 7 1 br1
rlabel metal2 50 7 50 7 8 br0
rlabel polycontact 29 49 29 49 1 Q
rlabel polycontact 25 42 25 42 1 Q_bar
<< end >>

0
technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag → technology/scn4m_subm/mag_lib/dummy_cell_2rw.mag
View File

0
technology/scn4m_subm/mag_lib/replica_cell_6t.mag → technology/scn4m_subm/mag_lib/replica_cell_1rw.mag
View File

147
technology/scn4m_subm/mag_lib/replica_cell_1w_1r.mag
View File

@ -1,147 +0,0 @@
magic
tech scmos
timestamp 1577067446
<< nwell >>
rect 0 46 54 75
<< pwell >>
rect 0 0 54 46
<< ntransistor >>
rect 14 33 16 37
rect 22 29 24 37
rect 30 29 32 37
rect 38 33 40 37
rect 14 17 16 23
rect 22 17 24 23
rect 30 17 32 23
rect 38 17 40 23
<< ptransistor >>
rect 22 54 24 57
rect 30 54 32 57
<< ndiffusion >>
rect 13 33 14 37
rect 16 33 17 37
rect 21 33 22 37
rect 17 29 22 33
rect 24 29 25 37
rect 29 29 30 37
rect 32 33 33 37
rect 37 33 38 37
rect 40 33 41 37
rect 32 29 37 33
rect 9 21 14 23
rect 13 17 14 21
rect 16 17 22 23
rect 24 17 25 23
rect 29 17 30 23
rect 32 17 38 23
rect 40 21 45 23
rect 40 17 41 21
<< pdiffusion >>
rect 21 54 22 57
rect 24 54 25 57
rect 29 54 30 57
rect 32 54 33 57
<< ndcontact >>
rect 9 33 13 37
rect 17 33 21 37
rect 25 29 29 37
rect 33 33 37 37
rect 41 33 45 37
rect 9 17 13 21
rect 25 17 29 23
rect 41 17 45 21
<< pdcontact >>
rect 17 54 21 58
rect 25 54 29 58
rect 33 54 37 58
<< psubstratepcontact >>
rect 25 9 29 13
<< nsubstratencontact >>
rect 25 68 29 72
<< polysilicon >>
rect 22 57 24 60
rect 30 57 32 60
rect 22 44 24 54
rect 30 51 32 54
rect 31 47 32 51
rect 14 37 16 44
rect 22 40 23 44
rect 22 37 24 40
rect 30 37 32 47
rect 38 37 40 44
rect 14 31 16 33
rect 38 31 40 33
rect 14 23 16 24
rect 22 23 24 29
rect 30 23 32 29
rect 38 23 40 24
rect 14 15 16 17
rect 22 15 24 17
rect 30 15 32 17
rect 38 15 40 17
<< polycontact >>
rect 27 47 31 51
rect 10 40 14 44
rect 23 40 27 44
rect 40 40 44 44
rect 12 24 16 28
rect 38 24 42 28
<< metal1 >>
rect 0 68 25 72
rect 29 68 54 72
rect 0 61 54 65
rect 10 44 14 61
rect 29 54 33 58
rect 17 51 20 54
rect 17 47 27 51
rect 17 37 20 47
rect 34 44 37 54
rect 27 40 37 44
rect 40 44 44 61
rect 34 37 37 40
rect 6 33 9 37
rect 45 33 48 37
rect 25 23 29 29
rect 25 13 29 17
rect 0 9 25 13
rect 29 9 54 13
rect 0 2 16 6
rect 20 2 34 6
rect 38 2 54 6
<< m2contact >>
rect 25 68 29 72
rect 25 54 29 58
rect 2 33 6 37
rect 48 33 52 37
rect 16 24 20 28
rect 34 24 38 28
rect 9 17 13 21
rect 41 17 45 21
rect 16 2 20 6
rect 34 2 38 6
<< metal2 >>
rect 2 37 6 72
rect 2 0 6 33
rect 9 21 13 72
rect 25 58 29 68
rect 9 0 13 17
rect 16 6 20 24
rect 34 6 38 24
rect 41 21 45 72
rect 41 0 45 17
rect 48 37 52 72
rect 48 0 52 33
<< comment >>
rect 0 0 54 70
<< labels >>
rlabel metal1 19 63 19 63 1 wl0
rlabel metal1 19 70 19 70 5 vdd
rlabel metal1 27 4 27 4 1 wl1
rlabel psubstratepcontact 27 11 27 11 1 gnd
rlabel metal2 4 7 4 7 2 bl0
rlabel metal2 11 7 11 7 1 bl1
rlabel metal2 43 7 43 7 1 br1
rlabel metal2 50 7 50 7 8 br0
rlabel polycontact 29 49 29 49 1 Q
rlabel polycontact 25 42 25 42 1 Q_bar
<< end >>

0
technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag → technology/scn4m_subm/mag_lib/replica_cell_2rw.mag
View File

35
technology/scn4m_subm/mag_lib/replica_cell_6t.ext
View File

@ -1,35 +0,0 @@
timestamp 1541443051
version 8.2
tech scmos
style TSMC0.35um(tsmc35)from:t11c
scale 1000 1 5
resistclasses 3700 2800 1018000 1018000 1 6000 6000 80 70 80 40
node "comment_0_0#" 0 0 0 0 bb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "br" 6 1.40998e-14 96 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3456 464 0 0 0 0
node "bl" 6 -8.88178e-16 40 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3200 432 0 0 0 0
node "wl" 115 -2.89546e-13 -8 12 p 0 0 0 0 0 0 0 0 0 0 1536 360 0 0 2496 344 0 0 0 0 0 0
node "a_36_40#" 140 -3.51719e-13 36 40 ndif 960 144 304 72 0 0 0 0 0 0 1984 424 0 0 2048 288 0 0 0 0 0 0
node "gnd" 41 -27.888 -32 -32 pw 1792 240 512 128 0 0 0 0 29600 696 0 0 0 0 2688 400 6400 864 0 0 0 0
equiv "gnd" "gnd"
node "vdd" 2517 2596 -32 116 nw 1216 208 1104 248 17600 576 0 0 0 0 2000 456 0 0 5632 736 256 64 0 0 0 0
cap "vdd" "br" 442.06
cap "bl" "wl" 189.768
cap "gnd" "br" 698.471
cap "bl" "a_36_40#" 29.396
cap "wl" "a_36_40#" 108.364
cap "bl" "vdd" 239.22
cap "bl" "gnd" 712.11
cap "wl" "vdd" 108.364
cap "wl" "gnd" 1198.41
cap "bl" "br" 27.492
cap "a_36_40#" "vdd" 981.901
cap "wl" "br" 189.768
cap "a_36_40#" "gnd" 401.284
cap "vdd" "gnd" 1390.52
cap "a_36_40#" "br" 17.59
fet nfet 96 12 97 13 128 48 "gnd" "wl" 16 0 "br" 16 0 "vdd" 16 0
fet nfet 40 12 41 13 128 48 "gnd" "wl" 16 0 "bl" 16 0 "a_36_40#" 16 0
fet nfet 116 40 117 41 256 80 "gnd" "a_36_40#" 16 0 "vdd" 32 0 "gnd" 32 0
fet nfet 28 40 29 41 256 80 "gnd" "vdd" 16 0 "gnd" 32 0 "a_36_40#" 32 0
fet pfet 108 148 109 149 192 56 "vdd" "a_36_40#" 32 0 "vdd" 24 0
fet pfet 28 148 29 149 192 56 "vdd" "vdd" 32 0 "vdd" 12 0 "a_36_40#" 12 0

16
technology/scn4m_subm/mag_lib/replica_cell_6t.spice
View File

@ -1,16 +0,0 @@
* SPICE3 file created from replica_cell_6t.ext - technology: scmos
M1000 a_36_40# vdd vdd vdd pfet w=0.6u l=0.8u
+ ad=0.76p pd=3.6u as=2.76p ps=12.4u
** SOURCE/DRAIN TIED
M1001 vdd a_36_40# vdd vdd pfet w=0.8u l=0.6u
+ ad=0p pd=0u as=0p ps=0u
M1002 a_36_40# vdd gnd gnd nfet w=1.6u l=0.4u
+ ad=2.4p pd=7.2u as=4.48p ps=12u
M1003 gnd a_36_40# vdd gnd nfet w=1.6u l=0.4u
+ ad=0p pd=0u as=3.04p ps=10.4u
M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
+ ad=0p pd=0u as=0.8p ps=3.6u
M1005 vdd wl br gnd nfet w=0.8u l=0.4u
+ ad=0p pd=0u as=0.8p ps=3.6u
C0 vdd 0 2.60fF

6
technology/scn4m_subm/sp_lib/cell_6t.sp → technology/scn4m_subm/sp_lib/cell_1rw.sp vendored
View File

@ -1,7 +1,7 @@
*********************** "cell_6t" ******************************
.SUBCKT cell_6t bl br wl vdd gnd
* SPICE3 file created from cell_6t.ext - technology: scmos
*********************** "cell_1rw" ******************************
.SUBCKT cell_1rw bl br wl vdd gnd
* SPICE3 file created from cell_1rw.ext - technology: scmos
* Inverter 1
M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u

14
technology/scn4m_subm/sp_lib/cell_1w_1r.sp vendored
View File

@ -1,14 +0,0 @@
.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u
MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u
MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u
MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u
MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u
.ENDS

4
technology/scn4m_subm/sp_lib/dummy_cell_6t.sp → technology/scn4m_subm/sp_lib/dummy_cell_1rw.sp vendored
View File

@ -1,6 +1,6 @@
*********************** "dummy_cell_6t" ******************************
.SUBCKT dummy_cell_6t bl br wl vdd gnd
*********************** "dummy_cell_1rw" ******************************
.SUBCKT dummy_cell_1rw bl br wl vdd gnd
* Inverter 1
M1000 Q Q_bar vdd vdd p w=0.6u l=0.8u

14
technology/scn4m_subm/sp_lib/dummy_cell_1w_1r.sp vendored
View File

@ -1,14 +0,0 @@
.SUBCKT dummy_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
MM9 RA_to_R_right wl1 br1_noconn gnd n w=1.2u l=0.4u
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u
MM6 RA_to_R_left wl1 bl1_noconn gnd n w=1.2u l=0.4u
MM5 Q wl0 bl0_noconn gnd n w=0.8u l=0.4u
MM4 Q_bar wl0 br0_noconn gnd n w=0.8u l=0.4u
MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u
MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u
MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u
MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u
.ENDS

6
technology/scn4m_subm/sp_lib/replica_cell_6t.sp → technology/scn4m_subm/sp_lib/replica_cell_1rw.sp vendored
View File

@ -1,7 +1,7 @@
*********************** "cell_6t" ******************************
.SUBCKT replica_cell_6t bl br wl vdd gnd
* SPICE3 file created from cell_6t.ext - technology: scmos
*********************** "cell_1rw" ******************************
.SUBCKT replica_cell_1rw bl br wl vdd gnd
* SPICE3 file created from cell_1rw.ext - technology: scmos
* Inverter 1
M1000 Q vdd vdd vdd p w=0.6u l=0.8u

14
technology/scn4m_subm/sp_lib/replica_cell_1w_1r.sp vendored
View File

@ -1,14 +0,0 @@
.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u
MM1 Q vdd gnd gnd n w=1.6u l=0.4u
MM0 vdd Q gnd gnd n w=1.6u l=0.4u
MM3 Q vdd vdd vdd p w=0.6u l=0.4u
MM2 vdd Q vdd vdd p w=0.6u l=0.4u
.ENDS

46
technology/scn4m_subm/sue_lib/cell_6t.sue
View File

@ -1,46 +0,0 @@
# SUE version MMI_SUE5.0.7
proc SCHEMATIC_cell_6t {} {
make inout -name BL -origin {190 360}
make inout -name BR -origin {830 360}
make input -name WL -origin {240 120}
make global -orient RXY -name vdd -origin {520 160}
make global -name gnd -origin {510 600}
make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230}
make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230}
make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360}
make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360}
make nmos -W 2.4u -L 0.6u -origin {630 490}
make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490}
make_wire 630 550 630 530
make_wire 400 530 400 550
make_wire 400 190 400 170
make_wire 630 170 630 190
make_wire 400 360 400 270
make_wire 310 360 400 360
make_wire 630 360 630 450
make_wire 630 360 700 360
make_wire 270 300 270 120
make_wire 270 120 740 120
make_wire 740 120 740 300
make_wire 230 360 190 360
make_wire 780 360 830 360
make_wire 510 550 400 550
make_wire 510 550 630 550
make_wire 510 550 510 600
make_wire 520 170 400 170
make_wire 520 170 630 170
make_wire 520 160 520 170
make_wire 240 120 270 120
make_wire 460 290 630 290
make_wire 460 290 460 490
make_wire 460 290 460 230
make_wire 630 290 630 360
make_wire 630 290 630 270
make_wire 570 420 400 420
make_wire 570 420 570 490
make_wire 570 420 570 230
make_wire 400 420 400 360
make_wire 400 420 400 450
}

84
technology/scn4m_subm/sue_lib/ms_flop.sue
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@ -1,84 +0,0 @@
# SUE version MMI_SUE5.0.7
proc SCHEMATIC_ms_flop {} {
make pmos -orient R90X -W 1.8u -L 0.6u -origin {40 250}
make nmos -orient R270 -W 0.9u -L 0.6u -origin {40 380}
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {-270 540}
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {310 310}
make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {430 730}
make pmos -orient R90X -W 1.8u -L 0.6u -origin {190 670}
make nmos -orient R270 -W 0.9u -L 0.6u -origin {190 780}
make input -name clk -origin {-380 540}
make input -name din -origin {-370 320}
make pmos -orient R90X -W 1.8u -L 0.6u -origin {720 250}
make nmos -orient R270 -W 0.9u -L 0.6u -origin {720 380}
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {990 310}
make pmos -orient R90X -W 1.8u -L 0.6u -origin {870 670}
make nmos -orient R270 -W 0.9u -L 0.6u -origin {870 780}
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {620 540}
make output -name dout -origin {1410 310}
make output -name dout_bar -origin {1430 930}
make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {1110 730}
make_wire -330 160 40 160
make_wire 40 160 40 190
make_wire -370 320 0 320
make_wire 360 310 480 310
make_wire 460 730 480 730
make_wire 230 730 380 730
make_wire 100 310 100 720
make_wire 100 720 150 720
make_wire 100 310 80 310
make_wire 100 310 280 310
make_wire 0 250 0 320
make_wire 0 320 0 380
make_wire 80 250 80 310
make_wire 80 310 80 380
make_wire 40 440 40 540
make_wire -330 840 190 840
make_wire 230 670 230 730
make_wire 230 730 230 780
make_wire 150 670 150 720
make_wire 150 720 150 780
make_wire 190 540 190 610
make_wire -330 540 -330 840
make_wire -220 540 40 540
make_wire 40 540 190 540
make_wire -380 540 -330 540
make_wire -330 540 -300 540
make_wire -330 540 -330 160
make_wire 720 160 720 190
make_wire 1140 730 1160 730
make_wire 780 310 780 720
make_wire 780 720 830 720
make_wire 780 310 760 310
make_wire 780 310 960 310
make_wire 680 320 680 380
make_wire 760 250 760 310
make_wire 760 310 760 380
make_wire 720 440 720 540
make_wire 910 670 910 730
make_wire 910 730 910 780
make_wire 830 670 830 720
make_wire 830 720 830 780
make_wire 870 540 870 610
make_wire 720 540 870 540
make_wire 670 540 720 540
make_wire 480 310 480 730
make_wire 1160 310 1160 730
make_wire 530 540 530 160
make_wire 530 160 720 160
make_wire 530 540 190 540
make_wire 530 540 590 540
make_wire 530 540 530 840
make_wire 530 840 870 840
make_wire 680 310 480 310
make_wire 680 310 680 250
make_wire 680 310 680 320
make_wire 950 730 910 730
make_wire 950 730 1060 730
make_wire 1040 310 1160 310
make_wire 1160 310 1410 310
make_wire 950 930 1430 930
make_wire 950 730 950 930
}

49
technology/scn4m_subm/sue_lib/replica_cell_6t.sue
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@ -1,49 +0,0 @@
# SUE version MMI_SUE5.0.7
proc SCHEMATIC_replica_cell_6t {} {
make inout -name BL -origin {190 360}
make inout -name BR -origin {830 360}
make input -name WL -origin {240 120}
make global -orient RXY -name vdd -origin {520 160}
make global -name gnd -origin {510 600}
make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230}
make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230}
make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360}
make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360}
make nmos -W 2.4u -L 0.6u -origin {630 490}
make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490}
make_wire 630 550 630 530
make_wire 400 530 400 550
make_wire 400 190 400 170
make_wire 630 170 630 190
make_wire 400 360 400 270
make_wire 630 360 630 450
make_wire 630 360 700 360
make_wire 270 300 270 120
make_wire 270 120 740 120
make_wire 740 120 740 300
make_wire 230 360 190 360
make_wire 780 360 830 360
make_wire 510 550 400 550
make_wire 510 550 630 550
make_wire 510 550 510 600
make_wire 520 170 400 170
make_wire 520 170 630 170
make_wire 520 160 520 170
make_wire 240 120 270 120
make_wire 460 290 630 290
make_wire 460 290 460 490
make_wire 460 290 460 230
make_wire 630 290 630 360
make_wire 630 290 630 270
make_wire 570 420 400 420
make_wire 570 420 570 490
make_wire 570 420 570 230
make_wire 400 420 400 360
make_wire 400 420 400 450
make_wire 320 360 320 550
make_wire 320 550 400 550
make_wire 320 360 310 360
make_wire 320 360 400 360
}

52
technology/scn4m_subm/sue_lib/sense_amp.sue
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@ -1,52 +0,0 @@
# SUE version MMI_SUE5.0.7
proc SCHEMATIC_sense_amp {} {
make inout -name BL -origin {260 10}
make global -orient RXY -name vdd -origin {490 170}
make global -name gnd -origin {480 660}
make input -name sclk -origin {180 610}
make nmos -W 3.9u -L 0.6u -origin {600 500}
make nmos -orient RX -W 3.9u -L 0.6u -origin {370 500}
make pmos -orient RY -W 3u -L 0.6u -origin {600 240}
make pmos -orient RXY -W 3u -L 0.6u -origin {370 240}
make nmos -W 3.9u -L 0.6u -origin {480 610}
make inout -name BR -origin {710 20}
make pmos -W 3.9u -L 0.6u -origin {710 90}
make pmos -orient RX -W 3.9u -L 0.6u -origin {260 90}
make output -orient RXY -name dout -origin {110 370}
make_wire 600 560 600 540
make_wire 370 540 370 560
make_wire 370 200 370 180
make_wire 600 180 600 200
make_wire 490 180 370 180
make_wire 490 180 600 180
make_wire 490 170 490 180
make_wire 430 300 600 300
make_wire 430 300 430 500
make_wire 430 300 430 240
make_wire 600 300 600 280
make_wire 540 430 370 430
make_wire 540 430 540 500
make_wire 540 430 540 240
make_wire 370 430 370 460
make_wire 480 560 600 560
make_wire 480 560 370 560
make_wire 480 560 480 570
make_wire 480 650 480 660
make_wire 420 610 180 610
make_wire 650 90 320 90
make_wire 600 360 710 360
make_wire 710 360 710 130
make_wire 600 360 600 300
make_wire 600 360 600 460
make_wire 370 370 260 370
make_wire 260 370 260 130
make_wire 370 370 370 430
make_wire 370 370 370 280
make_wire 260 10 260 50
make_wire 710 20 710 50
make_wire 320 90 180 90
make_wire 180 90 180 610
make_wire 110 370 260 370
}

37
technology/scn4m_subm/sue_lib/tri_gate.sue
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@ -1,37 +0,0 @@
# SUE version MMI_SUE5.0.7
proc SCHEMATIC_tri_gate {} {
make global -orient RXY -name vdd -origin {630 150}
make global -name gnd -origin {630 570}
make input -name tri_in -origin {320 340}
make output -name tri_out -origin {690 360}
make input -name en -origin {570 410}
make input -name en_bar -origin {570 310}
make nmos -W 1.2u -L 0.6u -origin {630 490}
make nmos -W 1.2u -L 0.6u -origin {630 410}
make pmos -orient RY -W 2.4u -L 0.6u -origin {630 310}
make pmos -orient RY -W 2.4u -L 0.6u -origin {630 230}
make pmos -orient RY -W 2.4u -L 0.6u -origin {380 290}
make nmos -W 1.2u -L 0.6u -origin {380 400}
make_wire 570 490 470 490
make_wire 470 230 570 230
make_wire 630 550 380 550
make_wire 380 550 380 440
make_wire 630 550 630 570
make_wire 630 550 630 530
make_wire 630 170 380 170
make_wire 380 170 380 250
make_wire 630 170 630 190
make_wire 630 170 630 150
make_wire 320 340 320 400
make_wire 320 340 320 290
make_wire 380 340 470 340
make_wire 380 340 380 330
make_wire 380 340 380 360
make_wire 470 340 470 490
make_wire 470 340 470 230
make_wire 630 360 630 350
make_wire 630 360 630 370
make_wire 630 360 690 360
}

44
technology/scn4m_subm/sue_lib/write_driver.sue
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@ -1,44 +0,0 @@
# SUE version MMI_SUE5.0.7
proc SCHEMATIC_write_driver {} {
make inout -name BL -origin {550 260}
make inout -name BR -origin {830 250}
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {280 520}
make nand2 -WP 2.1u -WN 2.1u -origin {90 360}
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {270 360}
make nmos -W 3.6u -L 0.6u -origin {830 410}
make nmos -W 3.6u -L 0.6u -origin {710 610}
make global -name gnd -origin {710 690}
make nand2 -WP 2.1u -WN 2.1u -origin {90 520}
make nmos -W 3.6u -L 0.6u -origin {550 410}
make input -name wen -origin {-290 340}
make input -name din -origin {-290 380}
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {-80 540}
make_wire 160 360 240 360
make_wire 830 250 830 370
make_wire 550 260 550 370
make_wire 550 450 550 560
make_wire 550 560 710 560
make_wire 710 560 710 570
make_wire 710 560 830 560
make_wire 830 560 830 450
make_wire 710 650 710 690
make_wire 250 520 160 520
make_wire 770 410 770 520
make_wire 770 520 330 520
make_wire 320 360 490 360
make_wire 490 360 490 410
make_wire -180 380 -290 380
make_wire -180 380 70 380
make_wire -180 540 -110 540
make_wire -180 380 -180 540
make_wire -30 540 70 540
make_wire 20 340 20 500
make_wire 20 500 70 500
make_wire 20 340 70 340
make_wire -240 340 -240 610
make_wire -240 610 650 610
make_wire -240 340 20 340
make_wire -240 340 -290 340
}

6
technology/scn4m_subm/tech/tech.py
View File

@ -33,12 +33,6 @@ cell_properties = cell_properties()
cell_properties.bitcell.mirror.x = True
cell_properties.bitcell.mirror.y = False
cell_properties.names["bitcell_1port"] = "cell_6t"
cell_properties.names["dummy_bitcell_1port"] = "dummy_cell_6t"
cell_properties.names["replcia_bitcell_1port"] = "replica_cell_6t"
cell_properties.names["bitcell_2port"] = "cell_2rw"
cell_properties.names["dummy_bitcell_2port"] = "dummy_cell_2rw"
cell_properties.names["replica_bitcell_2port"] = "replica_cell_2rw"
###################################################
# Custom cell properties