mirror of https://github.com/VLSIDA/OpenRAM.git
Fix missing update for left RBL offset
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@ -440,7 +440,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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else:
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offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(bit, -self.rbl[0] - 1)
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self.replica_col_insts[len(self.left_rbl) + bit].place(offset)
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self.replica_col_insts[self.rbl[0] + bit].place(offset)
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# Replica dummy rows
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# Add the dummy rows even if we aren't adding the replica column to this bitcell array
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