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sky130 rba done

This commit is contained in:
jcirimel 2020-09-30 07:34:05 -07:00
parent 3dd72cdeac
commit 7cbf456a4f
10 changed files with 1949 additions and 97 deletions
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4
compiler/custom/s8_col_end.py
View File

@ -21,8 +21,8 @@ class s8_col_end(design.design):
type_list = []
if version == "colend":
self.name = "s8sram16x16_colend"
structure = "s8sram16x16_colend\x00"
self.name = "s8sram16x16_colenda"
structure = "s8sram16x16_colenda\x00"
elif version == "colend_p_cent":
self.name = "s8sram16x16_colend_p_cent"
structure = "s8sram16x16_colend_p_cent\x00"

2
compiler/custom/s8_corner.py
View File

@ -27,7 +27,7 @@ class s8_corner(design.design):
elif location == "ll":
self.name = "s8sram16x16_cornera"
elif location == "lr":
self.name = "s8sram16x16_cornerb"
self.name = "s8sram16x16_cornera"
else:
debug.error("Invalid s8_corner location", -1)
design.design.__init__(self, name=self.name)

18
compiler/custom/s8_replica_bitcell.py
View File

@ -33,14 +33,26 @@ class replica_bitcell(design.design):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
if not OPTS.netlist_only:
(width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"])
(self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"],
layer["mem"],
"s8sram_cell\x00")
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
else:
(width,height) = (0,0)
pin_map = []
def __init__(self, name=""):
def __init__(self, version, name=""):
# Ignore the name argument
if version == "opt1":
self.name = "s8sram_cell_opt1"
self.border_structure = "s8sram_cell"
elif version == "opt1a":
self.name = "s8sram_cell_opt1a"
self.border_structure = "s8sram_cell"
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
design.design.__init__(self, "replica_cell_6t")
debug.info(2, "Create replica bitcell object")

3
compiler/modules/bitcell_array.py
View File

@ -58,9 +58,6 @@ class bitcell_array(bitcell_base_array):
self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
def create_instances(self):
""" Create the module instances used in this design """

34
compiler/modules/dummy_array.py
View File

@ -5,6 +5,8 @@
#
from bitcell_base_array import bitcell_base_array
from sram_factory import factory
from tech import GDS,layer,drc,parameter,cell_properties
from tech import cell_properties as props
from globals import OPTS
@ -38,21 +40,33 @@ class dummy_array(bitcell_base_array):
def add_modules(self):
""" Add the modules used in this design """
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell))
self.cell = factory.create(module_type="bitcell")
else:
self.dummy_cell = factory.create(module_type="s8_bitcell", version = "opt1")
self.dummy_cell2 = factory.create(module_type="s8_bitcell", version = "opt1a")
self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap"))
self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap_p"))
self.cell = factory.create(module_type="s8_bitcell", version = "opt1")
self.add_mod(self.dummy_cell2)
self.add_mod(self.dummy_cell)
self.cell = factory.create(module_type="bitcell")
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.dummy_cell)
self.connect_inst(self.get_bitcell_pins(row, col))
if not props.compare_ports(props.bitcell_array.use_custom_cell_arrangement):
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.dummy_cell)
self.connect_inst(self.get_bitcell_pins(row, col))
else:
from tech import custom_cell_arrangement
custom_cell_arrangement(self)
def input_load(self):
wl_wire = self.gen_wl_wire()
return wl_wire.return_input_cap()

181
compiler/modules/replica_bitcell_array.py
View File

@ -45,15 +45,11 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
debug.check(sum(rbl) <= len(self.all_ports),
"Invalid number of RBLs for port configuration.")
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
# Two dummy rows plus replica even if we don't add the column
self.extra_rows = 2 + sum(rbl)
# Two dummy cols plus replica if we add the column
self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl
else:
self.extra_rows = 0
self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl
# Two dummy rows plus replica even if we don't add the column
self.extra_rows = 2 + sum(rbl)
# Two dummy cols plus replica if we add the column
self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
@ -123,15 +119,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
end_caps_enabled = cell_properties.bitcell.end_caps
except AttributeError:
end_caps_enabled = False
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
# Dummy row
self.dummy_row = factory.create(module_type="dummy_array",
self.dummy_row = factory.create(module_type="dummy_array",
cols=self.column_size,
rows=1,
# dummy column + left replica column
column_offset=1 + self.add_left_rbl,
mirror=0)
self.add_mod(self.dummy_row)
self.add_mod(self.dummy_row)
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
# Dummy Row or Col Cap, depending on bitcell array properties
col_cap_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
@ -164,6 +160,25 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
mirror=(self.left_rbl + 1) %2)
self.add_mod(self.row_cap_right)
else:
# Dummy Row or Col Cap, depending on bitcell array properties
col_cap_module_type = ("s8_col_cap_array" if end_caps_enabled else "dummy_array")
self.col_cap_top = factory.create(module_type=col_cap_module_type,
cols=self.column_size,
rows=1,
# dummy column + left replica column(s)
column_offset=1 + self.add_left_rbl,
mirror=0,
location="top")
self.add_mod(self.col_cap_top)
self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
cols=self.column_size,
rows=1,
# dummy column + left replica column(s)
column_offset=1 + self.add_left_rbl,
mirror=0,
location="bottom")
self.add_mod(self.col_cap_bottom)
# Dummy Col or Row Cap, depending on bitcell array properties
row_cap_module_type = ("s8_row_cap_array" if end_caps_enabled else "dummy_array")
@ -258,8 +273,15 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
self.all_dummy_row_wordline_names = [x for sl in self.dummy_row_wordline_names for x in sl]
for port in range(self.left_rbl + self.right_rbl):
wordline_names=["rbl_wl_{0}_{1}".format(x, port) for x in self.all_ports]
self.rbl_wordline_names.append(wordline_names)
if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
wordline_names=["rbl_wl_{0}_{1}".format(x, port) for x in self.all_ports]
self.rbl_wordline_names.append(wordline_names)
else:
for x in self.all_ports:
wordline_names = []
wordline_names.append("rbl_wl0_{0}_{1}".format(x, port))
wordline_names.append("rbl_wl1_{0}_{1}".format(x, port))
self.rbl_wordline_names.append(wordline_names)
self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
for port in self.all_ports:
@ -290,8 +312,11 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
def create_instances(self):
""" Create the module instances used in this design """
supplies = ["vdd", "gnd"]
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
self.supplies = ["vdd", "gnd"]
else:
self.supplies = ["vpwr", "vgnd"]
# Used for names/dimensions only
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
@ -302,52 +327,82 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
# Main array
self.bitcell_array_inst=self.add_inst(name="bitcell_array",
mod=self.bitcell_array)
self.connect_inst(self.all_bitline_names + self.all_wordline_names + supplies)
self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
# Replica columns
self.replica_col_insts = []
for port in range(self.add_left_rbl + self.add_right_rbl):
self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
mod=self.replica_columns[port]))
self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + supplies)
self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
# Dummy rows under the bitcell array (connected with with the replica cell wl)
self.dummy_row_replica_insts = []
# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
for port in range(self.left_rbl + self.right_rbl):
self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
mod=self.dummy_row))
self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + supplies)
mod=self.dummy_row))
self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + self.supplies)
# Top/bottom dummy rows or col caps
self.dummy_row_insts = []
self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
mod=self.col_cap))
self.connect_inst(self.all_bitline_names
+ self.dummy_row_wordline_names[0]
+ supplies)
self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
mod=self.col_cap))
self.connect_inst(self.all_bitline_names
+ self.dummy_row_wordline_names[1]
+ supplies)
# Left/right Dummy columns
self.dummy_col_insts = []
self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
mod=self.row_cap_left))
self.connect_inst(self.dummy_col_bitline_names[0] + self.replica_array_wordline_names + supplies)
self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
mod=self.row_cap_right))
self.connect_inst(self.dummy_col_bitline_names[1] + self.replica_array_wordline_names + supplies)
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
# Top/bottom dummy rows or col caps
self.dummy_row_insts = []
self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
mod=self.col_cap))
self.connect_inst(self.all_bitline_names
+ self.dummy_row_wordline_names[0]
+ self.supplies)
self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
mod=self.col_cap))
self.connect_inst(self.all_bitline_names
+ self.dummy_row_wordline_names[1]
+ self.supplies)
# Left/right Dummy columns
self.dummy_col_insts = []
self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
mod=self.row_cap_left))
self.connect_inst(self.dummy_col_bitline_names[0] + self.replica_array_wordline_names + self.supplies)
self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
mod=self.row_cap_right))
self.connect_inst(self.dummy_col_bitline_names[1] + self.replica_array_wordline_names + self.supplies)
else:
# Top/bottom dummy rows or col caps
self.dummy_row_insts = []
self.dummy_row_insts.append(self.add_inst(name="col_cap_bottom",
mod=self.col_cap_bottom))
self.connect_inst(self.all_bitline_names
+ self.supplies)
self.dummy_row_insts.append(self.add_inst(name="col_cap_top",
mod=self.col_cap_top))
self.connect_inst(self.all_bitline_names
+ self.supplies)
# Left/right Dummy columns
self.dummy_col_insts = []
self.dummy_col_insts.append(self.add_inst(name="row_cap_left",
mod=self.row_cap_left))
self.connect_inst(self.replica_array_wordline_names + self.supplies)
self.dummy_col_insts.append(self.add_inst(name="row_cap_right",
mod=self.row_cap_right))
self.connect_inst(self.replica_array_wordline_names + self.supplies)
def create_layout(self):
self.height = (self.row_size + self.extra_rows) * self.dummy_row.height
self.width = (self.column_size + self.extra_cols) * self.cell.width
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
self.height = (self.row_size + self.extra_rows) * self.dummy_row.height
self.width = (self.column_size + self.extra_cols) * self.cell.width
else:
self.width = self.row_cap_left.top_corner.width + self.row_cap_right.top_corner.width + (self.col_cap_top.colend1.width + self.col_cap_top.colend2.width) * (self.column_size + self.extra_cols) - self.col_cap_top.colend2.width
self.height = self.row_cap_left.height
# This is a bitcell x bitcell offset to scale
self.bitcell_offset = vector(self.cell.width, self.cell.height)
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
self.strap_offset = vector(0, 0)
self.col_end_offset = vector(self.cell.width, self.cell.height)
self.row_end_offset = vector(self.cell.width, self.cell.height)
else:
self.strap_offset = vector(self.replica_col_insts[0].mod.strap1.width, self.replica_col_insts[0].mod.strap1.height)
self.col_end_offset = vector(self.dummy_row_insts[0].mod.colend1.width, self.dummy_row_insts[0].mod.colend1.height)
self.row_end_offset = vector(self.dummy_col_insts[0].mod.rowend1.width, self.dummy_col_insts[0].mod.rowend1.height)
# Everything is computed with the main array at (0, 0) to start
self.bitcell_array_inst.place(offset=[0, 0])
@ -368,14 +423,23 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
def add_replica_columns(self):
""" Add replica columns on left and right of array """
end_caps_enabled = cell_properties.bitcell.end_caps
# Grow from left to right, toward the array
for bit in range(self.add_left_rbl):
offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - 1)
if not end_caps_enabled:
offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - 1) + self.strap_offset.scale(-self.add_left_rbl + bit, 0)
else:
offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(-self.add_left_rbl + bit, 0)
self.replica_col_insts[bit].place(offset)
# Grow to the right of the bitcell array, array outward
for bit in range(self.add_right_rbl):
offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - 1)
if not end_caps_enabled:
offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - 1) + self.strap_offset.scale(bit, -self.left_rbl - 1)
else:
offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(bit, -self.left_rbl - 1)
self.replica_col_insts[self.add_left_rbl + bit].place(offset)
# Replica dummy rows
@ -391,26 +455,42 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
def add_end_caps(self):
""" Add dummy cells or end caps around the array """
end_caps_enabled = cell_properties.bitcell.end_caps
# FIXME: These depend on the array size itself
# Far top dummy row (first row above array is NOT flipped)
flip_dummy = self.right_rbl % 2
dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul()
if not end_caps_enabled:
dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul()
else:
dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul()
self.dummy_row_insts[1].place(offset=dummy_row_offset,
mirror="MX" if flip_dummy else "R0")
# FIXME: These depend on the array size itself
# Far bottom dummy row (first row below array IS flipped)
flip_dummy = (self.left_rbl + 1) % 2
dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - 1 + flip_dummy)
if not end_caps_enabled:
dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - 1 + flip_dummy)
else:
dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - (self.col_end_offset.y/self.cell.height) + flip_dummy)
self.dummy_row_insts[0].place(offset=dummy_row_offset,
mirror="MX" if flip_dummy else "R0")
# Far left dummy col
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
dummy_col_offset = self.bitcell_offset.scale(-self.add_left_rbl - 1, -self.left_rbl - 1)
if not end_caps_enabled:
dummy_col_offset = self.bitcell_offset.scale(-self.add_left_rbl - 1, -self.left_rbl - 1)
else:
dummy_col_offset = self.bitcell_offset.scale(-(self.add_left_rbl*(1+self.strap_offset.x/self.cell.width)) - (self.row_end_offset.x/self.cell.width), -self.left_rbl - (self.col_end_offset.y/self.cell.height))
self.dummy_col_insts[0].place(offset=dummy_col_offset)
# Far right dummy col
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl, -self.left_rbl - 1) + self.bitcell_array_inst.lr()
if not end_caps_enabled:
dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl*(1+self.strap_offset.x/self.cell.width), -self.left_rbl - 1) + self.bitcell_array_inst.lr()
else:
dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl*(1+self.strap_offset.x/self.cell.width), -self.left_rbl - (self.col_end_offset.y/self.cell.height)) + self.bitcell_array_inst.lr()
self.dummy_col_insts[1].place(offset=dummy_col_offset)
def add_layout_pins(self):
@ -470,7 +550,8 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
# vdd/gnd are only connected in the perimeter cells
# replica column should only have a vdd/gnd in the dummy cell on top/bottom
supply_insts = self.dummy_col_insts + self.dummy_row_insts
for pin_name in ["vdd", "gnd"]:
for pin_name in self.supplies:
for inst in supply_insts:
pin_list = inst.get_pins(pin_name)
for pin in pin_list:

26
compiler/modules/replica_column.py
View File

@ -28,7 +28,10 @@ class replica_column(design.design):
self.right_rbl = rbl[1]
self.replica_bit = replica_bit
# left, right, regular rows plus top/bottom dummy cells
self.total_size = self.left_rbl + rows + self.right_rbl + 2
if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement):
self.total_size = self.left_rbl + rows + self.right_rbl + 2
else:
self.total_size = self.left_rbl + rows + self.right_rbl + 2
self.column_offset = column_offset
debug.check(replica_bit != 0 and replica_bit != rows,
@ -78,13 +81,14 @@ class replica_column(design.design):
self.add_pin_list(self.all_wordline_names, "INPUT")
else:
self.wordline_names = [[] for port in self.all_ports]
for row in range(self.rows):
for row in range(self.total_size):
for port in self.all_ports:
if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
else:
self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
if (row > 0 and row < self.total_size-1):
self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
self.add_pin_list(self.all_wordline_names, "INPUT")
@ -276,13 +280,13 @@ class replica_column(design.design):
width=self.width,
height=wl_pin.height())
# # Supplies are only connected in the ends
# for (index, inst) in self.cell_inst.items():
# for pin_name in ["vdd", "gnd"]:
# if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
# self.copy_power_pins(inst, pin_name)
# else:
# self.copy_layout_pin(inst, pin_name)
# Supplies are only connected in the ends
for (index, inst) in self.cell_inst.items():
for pin_name in ["vpwr", "vgnd"]:
if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
self.copy_power_pins(inst, pin_name)
else:
self.copy_layout_pin(inst, pin_name)
def get_bitline_names(self, port=None):
if port == None:

1768
compiler/tests/sram_1b_16_1rw_sky130.log
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missing_pin.gds
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10
sram_1b_16_1rw_sky130.log
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@ -15,12 +15,4 @@
[bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4
[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4
[bitcell_base_array/__init__]: Creating bitcell_array 4 x 4
ERROR: file hierarchy_spice.py: line 176: Connection mismatch:
Inst (4) -> Mod (6)
bl_0_0 -> bl0
br_0_0 -> bl1
vdd -> wl0
gnd -> wl1
-> vpwr
-> vgnd
[bitcell_base_array/__init__]: Creating dummy_array 1 x 4