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clk_pin is redundant in DFFs

This commit is contained in:
mrg 2020-11-13 16:23:27 -08:00
parent 620e271562
commit 01d191da40
5 changed files with 14 additions and 26 deletions
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30
compiler/base/custom_cell_properties.py
View File

@ -20,11 +20,8 @@ class _cell:
port_map = {}
for pin in port_order:
port_map[pin] = pin
self._pins = _pins(port_map)
else:
self._pins = _pins(port_map)
self._pins = _pins(port_map)
self._port_names = [getattr(self._pins, x) for x in self._port_order]
self._boundary_layer = boundary_layer
@property
@ -35,9 +32,8 @@ class _cell:
def hard_cell(self):
return self._hard_cell
@property
def port_names(self):
return self._port_names
return [getattr(self._pins, x) for x in self._port_order]
@property
def port_types(self):
@ -98,13 +94,7 @@ class _bitcell(_cell):
def storage_nets(self):
return self._storage_nets
class _dff(_cell):
def __init__(self, clk_pin, port_order, port_types, port_map=None, hard_cell=True):
super().__init__(port_order, port_types, port_map, hard_cell)
self.clk_pin = clk_pin
class cell_properties():
"""
This contains meta information about the custom designed cells. For
@ -139,14 +129,12 @@ class cell_properties():
self._nand2_dec = _cell(["A", "B", "C", "D", "Z", "vdd", "gnd"],
["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"])
self._dff = _dff("clk",
["D", "Q", "clk", "vdd", "gnd"],
["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
self._dff = _cell(["D", "Q", "clk", "vdd", "gnd"],
["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
self._dff_buf = _dff("clk",
["D", "Q", "Qb", "clk", "vdd", "gnd"],
["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"],
hard_cell=False)
self._dff_buf = _cell(["D", "Q", "Qb", "clk", "vdd", "gnd"],
["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"],
hard_cell=False)
self._write_driver = _cell(['din', 'bl', 'br', 'en', 'vdd', 'gnd'],
["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
@ -155,7 +143,7 @@ class cell_properties():
["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
self._bitcell_1port = _bitcell(["bl", "br", "wl", "vdd", "gnd"],
["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND<"])
self._bitcell_2port = _bitcell(["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"],
["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"])

4
compiler/base/design.py
View File

@ -37,8 +37,8 @@ class design(hierarchy_design):
prop = getattr(props, name)
if prop.hard_cell:
# The pins get added from the spice file
debug.check(prop.port_names == self.pins,
"Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names, self.pins))
debug.check(prop.port_names() == self.pins,
"Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names(), self.pins))
self.add_pin_types(prop.port_types)
(width, height) = utils.get_libcell_size(self.cell_name,

2
compiler/bitcells/bitcell_base.py
View File

@ -22,7 +22,7 @@ class bitcell_base(design.design):
design.design.__init__(self, name)
if prop:
self.pins = prop.port_names
self.pins = prop.port_names()
self.add_pin_types(prop.port_types)
self.nets_match = self.do_nets_exist(prop.storage_nets)
self.mirror = prop.mirror

2
compiler/custom/dff.py
View File

@ -18,7 +18,7 @@ class dff(design.design):
def __init__(self, name="dff"):
super().__init__(name)
self.clk_pin = props.dff.clk_pin
self.clk_pin = props.dff.pin.clk
def analytical_power(self, corner, load):
"""Returns dynamic and leakage power. Results in nW"""

2
compiler/modules/dff_buf.py
View File

@ -72,7 +72,7 @@ class dff_buf(design.design):
self.add_mod(self.inv2)
def add_pins(self):
self.add_pin_list(props.dff_buf.port_names,
self.add_pin_list(props.dff_buf.port_names(),
props.dff_buf.port_types)
def create_instances(self):