mirror of https://github.com/VLSIDA/OpenRAM.git
removed references to technology name
This commit is contained in:
jcirimel
parent
de33ab3761
commit
fb6a665514
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@ -5,6 +5,7 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from globals import OPTS
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class _pins:
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def __init__(self, pin_dict):
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@ -107,6 +108,10 @@ class _dff_buff_array:
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self.use_custom_ports = use_custom_ports
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self.add_body_contacts = add_body_contacts
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class _bitcell_array:
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def __init__(self, use_custom_cell_arrangement):
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self.use_custom_cell_arrangement = use_custom_cell_arrangement
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class cell_properties():
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"""
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This contains meta information about the custom designed cells. For
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@ -134,11 +139,14 @@ class cell_properties():
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'bl' : 'bl',
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'br' : 'br',
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'en' : 'en'})
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self._sense_amp = _cell({'bl' : 'bl',
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'br' : 'br',
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'dout' : 'dout',
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'en' : 'en'})
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self._bitcell_array = _bitcell_array(use_custom_cell_arrangement = [])
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@property
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def bitcell(self):
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return self._bitcell
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@ -162,3 +170,15 @@ class cell_properties():
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@property
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def sense_amp(self):
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return self._sense_amp
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@property
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def bitcell_array(self):
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return self._bitcell_array
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def use_custom_bitcell_array(self, port_list):
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use_custom_arrangement = False
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for ports in port_list:
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if ports == "{}R_{}W_{}RW".format(OPTS.num_r_ports, OPTS.num_w_ports, OPTS.num_rw_ports):
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use_custom_arrangement = True
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break
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return use_custom_arrangement
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@ -8,6 +8,7 @@
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from bitcell_base_array import bitcell_base_array
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from s8_corner import s8_corner
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from tech import drc, spice
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from tech import cell_properties as props
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from globals import OPTS
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from sram_factory import factory
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@ -46,7 +47,7 @@ class bitcell_array(bitcell_base_array):
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def add_modules(self):
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""" Add the modules used in this design """
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if OPTS.tech_name != "sky130":
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if not props.use_custom_bitcell_array(props.bitcell_array.use_custom_cell_arrangement):
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self.cell = factory.create(module_type="bitcell")
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self.add_mod(self.cell)
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@ -73,7 +74,7 @@ class bitcell_array(bitcell_base_array):
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst = {}
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if OPTS.tech_name != "sky130":
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if not props.use_custom_bitcell_array(props.bitcell_array.use_custom_cell_arrangement):
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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@ -81,44 +82,8 @@ class bitcell_array(bitcell_base_array):
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mod=self.cell)
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self.connect_inst(self.get_bitcell_pins(row, col))
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else:
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self.array_layout = []
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alternate_bitcell = 0
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for row in range(0,self.row_size):
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row_layout = []
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alternate_strap = 1
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for col in range(0,self.column_size):
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if alternate_bitcell == 1:
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row_layout.append(self.cell)
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self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
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mod=self.cell)
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else:
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row_layout.append(self.cell2)
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self.cell_inst[row, col]=self.add_inst(name="row_{}, col_{}_bitcell".format(row,col),
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mod=self.cell2)
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self.connect_inst(self.get_bitcell_pins(row, col))
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if col != self.column_size-1:
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if alternate_strap:
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row_layout.append(self.strap2)
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self.add_inst(name="row_{}, col_{}_wlstrap".format(row,col),
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mod=self.strap2)
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alternate_strap = 0
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else:
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row_layout.append(self.strap)
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self.add_inst(name="row_{}, col_{}_wlstrap".format(row,col),
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mod=self.strap)
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alternate_strap = 1
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self.connect_inst([])
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if alternate_bitcell == 0:
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alternate_bitcell = 1
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else:
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alternate_bitcell = 0
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self.array_layout.append(row_layout)
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from tech import custom_cell_arrangement
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custom_cell_arrangement(self)
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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@ -196,7 +196,7 @@ class bitcell_base_array(design.design):
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def place_array(self, name_template, row_offset=0):
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# We increase it by a well enclosure so the precharges don't overlap our wells
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if OPTS.tech_name != "sky130":
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if not cell_properties.use_custom_bitcell_array(cell_properties.bitcell_array.use_custom_cell_arrangement):
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width
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@ -222,18 +222,5 @@ class bitcell_base_array(design.design):
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yoffset += self.cell.height
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xoffset += self.cell.width
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else:
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self.height = self.row_size * self.cell.height
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self.width = self.column_size * self.cell.width + (self.column_size-1) * self.strap.width
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yoffset = 0.0
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for row in range(0, len(self.array_layout)):
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xoffset = 0.0
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for col in range(0, len(self.array_layout[row])):
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inst = self.insts[col + row*len(self.array_layout[row])]
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inst.place(offset=[xoffset, yoffset])
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xoffset += inst.width
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yoffset += self.cell.height
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from tech import custom_cell_placement
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custom_cell_placement(self)
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