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OpenRAM
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Change custom cells to use set_ports setter

This commit is contained in:
mrg 2020-11-14 07:15:27 -08:00
parent 1624d50ca9
commit 2f994b8c0a
6 changed files with 36 additions and 25 deletions
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31
compiler/base/custom_cell_properties.py
View File

@ -10,18 +10,27 @@ class _cell:
def __init__(self, port_order, port_types, port_map=None, hard_cell=True, boundary_layer="boundary"):
# Specifies if this is a hard (i.e. GDS) cell
self._hard_cell = hard_cell
# Specifies the order in the spice modules
self._port_order = port_order
self._boundary_layer = boundary_layer
# Specifies the port directions
self._port_types = {x: y for (x, y) in zip(port_order, port_types)}
self._port_types_map = {x: y for (x, y) in zip(port_order, port_types)}
# Specifies a map from OpenRAM names to cell names
# by default it is 1:1
if not port_map:
port_map = {x: x for x in port_order}
self.set_ports(port_order, port_map)
def set_ports(self,
port_order,
port_map):
# Update mapping of names
self._pins = _pins(port_map)
self._boundary_layer = boundary_layer
self._port_order = port_order
# Update ordered name list
self._port_names = [getattr(self._pins, x) for x in self._port_order]
# Update ordered type list
self._port_types = [self._port_types_map[x] for x in port_order]
@property
def pin(self):
return self._pins
@ -29,12 +38,14 @@ class _cell:
@property
def hard_cell(self):
return self._hard_cell
def port_names(self):
return [getattr(self._pins, x) for x in self._port_order]
@property
def port_names(self):
return self._port_names
@property
def port_types(self):
return [self._port_types[x] for x in self._port_order]
return self._port_types
@property
def boundary_layer(self):

6
compiler/base/design.py
View File

@ -37,9 +37,9 @@ class design(hierarchy_design):
prop = getattr(props, name)
if prop.hard_cell:
# The pins get added from the spice file
debug.check(prop.port_names() == self.pins,
"Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names(), self.pins))
self.add_pin_types(prop.port_types())
debug.check(prop.port_names == self.pins,
"Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names, self.pins))
self.add_pin_types(prop.port_types)
(width, height) = utils.get_libcell_size(self.cell_name,
GDS["unit"],

4
compiler/bitcells/bitcell_base.py
View File

@ -22,8 +22,8 @@ class bitcell_base(design.design):
design.design.__init__(self, name)
if prop:
self.pins = prop.port_names()
self.add_pin_types(prop.port_types())
self.pins = prop.port_names
self.add_pin_types(prop.port_types)
self.storage_nets = prop.storage_nets
self.nets_match = self.do_nets_exist(prop.storage_nets)
self.mirror = prop.mirror

4
compiler/modules/dff_buf.py
View File

@ -72,8 +72,8 @@ class dff_buf(design.design):
self.add_mod(self.inv2)
def add_pins(self):
self.add_pin_list(props.dff_buf.port_names(),
props.dff_buf.port_types())
self.add_pin_list(props.dff_buf.port_names,
props.dff_buf.port_types)
def create_instances(self):
self.dff_inst=self.add_inst(name="dff_buf_dff",

8
compiler/tests/30_openram_back_end_test.py
View File

@ -8,14 +8,14 @@
#
import unittest
from testutils import *
import sys, os,re,shutil
import sys, os, re, shutil
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
import getpass
class openram_back_end_test(openram_test):
def runTest(self):
@ -25,12 +25,12 @@ class openram_back_end_test(openram_test):
debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.")
out_file = "testsram"
out_path = "/tmp/testsram_{0}_{1}_{2}/".format(OPTS.tech_name,getpass.getuser(),os.getpid())
out_path = "/tmp/testsram_{0}_{1}_{2}/".format(OPTS.tech_name, getpass.getuser(), os.getpid())
# make sure we start without the files existing
if os.path.exists(out_path):
shutil.rmtree(out_path, ignore_errors=True)
self.assertEqual(os.path.exists(out_path),False)
self.assertEqual(os.path.exists(out_path), False)
try:
os.makedirs(out_path, 0o0750)

8
compiler/tests/30_openram_front_end_test.py
View File

@ -8,14 +8,14 @@
#
import unittest
from testutils import *
import sys, os,re,shutil
import sys, os, re, shutil
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
import getpass
class openram_front_end_test(openram_test):
def runTest(self):
@ -25,12 +25,12 @@ class openram_front_end_test(openram_test):
debug.info(1, "Testing top-level front-end openram.py with 2-bit, 16 word SRAM.")
out_file = "testsram"
out_path = "/tmp/testsram_{0}_{1}_{2}".format(OPTS.tech_name,getpass.getuser(),os.getpid())
out_path = "/tmp/testsram_{0}_{1}_{2}".format(OPTS.tech_name, getpass.getuser(), os.getpid())
# make sure we start without the files existing
if os.path.exists(out_path):
shutil.rmtree(out_path, ignore_errors=True)
self.assertEqual(os.path.exists(out_path),False)
self.assertEqual(os.path.exists(out_path), False)
try:
os.makedirs(out_path, 0o0750)