Port type order generated on the fly

compiler/base/custom_cell_properties.py

@@ -13,13 +13,11 @@ class _cell:
         # Specifies the order in the spice modules
         self._port_order = port_order
         # Specifies the port directions
-        self._port_types = port_types
+        self._port_types = {x: y for (x, y) in zip(port_order, port_types)}
         # Specifies a map from OpenRAM names to cell names
         # by default it is 1:1
         if not port_map:
-            port_map = {}
-            for pin in port_order:
-                port_map[pin] = pin
+            port_map = {x: x for x in port_order}
         self._pins = _pins(port_map)
 
         self._boundary_layer = boundary_layer
@@ -35,9 +33,8 @@ class _cell:
     def port_names(self):
         return [getattr(self._pins, x) for x in self._port_order]
 
-    @property
     def port_types(self):
-        return self._port_types
+        return [self._port_types[x] for x in self._port_order]
 
     @property
     def boundary_layer(self):
@@ -143,7 +140,7 @@ class cell_properties():
                                 ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
 
         self._bitcell_1port = _bitcell(["bl", "br", "wl", "vdd", "gnd"],
-                                       ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND<"])
+                                       ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
 
         self._bitcell_2port = _bitcell(["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"],
                                        ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"])

compiler/base/design.py

@@ -39,7 +39,7 @@ class design(hierarchy_design):
                 # The pins get added from the spice file
                 debug.check(prop.port_names() == self.pins,
                             "Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names(), self.pins))
-                self.add_pin_types(prop.port_types)
+                self.add_pin_types(prop.port_types())
             
                 (width, height) = utils.get_libcell_size(self.cell_name,
                                                          GDS["unit"],

compiler/bitcells/bitcell_base.py

@@ -23,7 +23,7 @@ class bitcell_base(design.design):
 
         if prop:
             self.pins = prop.port_names()
-            self.add_pin_types(prop.port_types)
+            self.add_pin_types(prop.port_types())
             self.nets_match = self.do_nets_exist(prop.storage_nets)
             self.mirror = prop.mirror
             self.end_caps = prop.end_caps

compiler/modules/dff_buf.py

@@ -73,7 +73,7 @@ class dff_buf(design.design):
 
     def add_pins(self):
         self.add_pin_list(props.dff_buf.port_names(),
-                          props.dff_buf.port_types)
+                          props.dff_buf.port_types())
 
     def create_instances(self):
         self.dff_inst=self.add_inst(name="dff_buf_dff",