mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 updates
This commit is contained in:
mrg
parent
b0d2946c80
commit
d916322b74
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@ -13,6 +13,7 @@ import debug
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from globals import OPTS
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import logical_effort
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class sense_amp_array(design.design):
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"""
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Array of sense amplifiers to read the bitlines through the column mux.
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@ -69,7 +70,7 @@ class sense_amp_array(design.design):
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self.DRC_LVS()
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def add_pins(self):
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for i in range(0,self.word_size):
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for i in range(0, self.word_size):
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self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT")
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self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT")
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self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT")
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@ -88,7 +89,7 @@ class sense_amp_array(design.design):
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def create_sense_amp_array(self):
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self.local_insts = []
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for i in range(0,self.word_size):
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for i in range(0, self.word_size):
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name = "sa_d{0}".format(i)
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self.local_insts.append(self.add_inst(name=name,
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@ -105,7 +106,7 @@ class sense_amp_array(design.design):
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else:
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amp_spacing = self.amp.width * self.words_per_row
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for i in range(0,self.word_size):
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for i in range(0, self.word_size):
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xoffset = amp_spacing * i
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# align the xoffset to the grid of bitcells. This way we
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@ -119,20 +120,19 @@ class sense_amp_array(design.design):
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mirror = ""
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amp_position = vector(xoffset, 0)
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self.local_insts[i].place(offset=amp_position,mirror=mirror)
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self.local_insts[i].place(offset=amp_position, mirror=mirror)
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def add_layout_pins(self):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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self.add_power_pin(name = "gnd",
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loc = inst.get_pin("gnd").center(),
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self.add_power_pin(name="gnd",
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loc=inst.get_pin("gnd").center(),
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start_layer="m2",
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vertical=True)
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self.add_power_pin(name = "vdd",
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loc = inst.get_pin("vdd").center(),
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self.add_power_pin(name="vdd",
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loc=inst.get_pin("vdd").center(),
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start_layer="m2",
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vertical=True)
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@ -157,16 +157,15 @@ class sense_amp_array(design.design):
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width=dout_pin.width(),
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height=dout_pin.height())
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def route_rails(self):
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# add sclk rail across entire array
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sclk = self.amp.get_pin(self.amp.en_name)
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sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1)
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sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0, 1)
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self.add_layout_pin(text=self.en_name,
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layer=sclk.layer,
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offset=sclk_offset,
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width=self.width,
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height=drc("minwidth_" + sclk.layer))
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layer=sclk.layer,
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offset=sclk_offset,
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width=self.width,
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height=drc("minwidth_" + sclk.layer))
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def input_load(self):
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return self.amp.input_load()
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@ -179,6 +178,6 @@ class sense_amp_array(design.design):
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the PMOS isolation TX"""
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from tech import parameter
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#Bitcell drain load being used to estimate PMOS drain load
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# Bitcell drain load being used to estimate PMOS drain load
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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return drain_load
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@ -5,21 +5,20 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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from tech import drc
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import debug
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class write_driver_array(design.design):
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"""
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Array of tristate drivers to write to the bitlines through the column mux.
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Dynamically generated write driver array of all bitlines.
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"""
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def __init__(self, name, columns, word_size,write_size=None):
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def __init__(self, name, columns, word_size, write_size=None):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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@ -31,7 +30,7 @@ class write_driver_array(design.design):
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self.words_per_row = int(columns / word_size)
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if self.write_size:
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self.num_wmasks = int(self.word_size/self.write_size)
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self.num_wmasks = int(self.word_size / self.write_size)
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self.create_netlist()
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if not OPTS.netlist_only:
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@ -97,9 +96,9 @@ class write_driver_array(design.design):
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self.driver_insts = {}
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w = 0
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windex=0
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for i in range(0,self.columns,self.words_per_row):
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for i in range(0, self.columns, self.words_per_row):
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name = "write_driver{}".format(i)
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index = int(i/self.words_per_row)
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index = int(i / self.words_per_row)
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self.driver_insts[index]=self.add_inst(name=name,
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mod=self.driver)
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@ -119,15 +118,14 @@ class write_driver_array(design.design):
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self.get_br_name() + "_{0}".format(index),
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self.en_name, "vdd", "gnd"])
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def place_write_array(self):
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from tech import cell_properties
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if self.bitcell.width > self.driver.width:
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self.driver_spacing = self.bitcell.width
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else:
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self.driver_spacing = self.driver.width
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for i in range(0,self.columns,self.words_per_row):
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index = int(i/self.words_per_row)
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for i in range(0, self.columns, self.words_per_row):
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index = int(i / self.words_per_row)
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xoffset = i * self.driver_spacing
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if cell_properties.bitcell.mirror.y and i % 2:
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@ -139,7 +137,6 @@ class write_driver_array(design.design):
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base = vector(xoffset, 0)
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self.driver_insts[index].place(offset=base, mirror=mirror)
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def add_layout_pins(self):
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for i in range(self.word_size):
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inst = self.driver_insts[i]
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@ -166,16 +163,16 @@ class write_driver_array(design.design):
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for n in ["vdd", "gnd"]:
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pin_list = self.driver_insts[i].get_pins(n)
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for pin in pin_list:
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self.add_power_pin(name = n,
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loc = pin.center(),
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self.add_power_pin(name=n,
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loc=pin.center(),
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vertical=True,
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start_layer = "m2")
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start_layer="m2")
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if self.write_size:
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for bit in range(self.num_wmasks):
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inst = self.driver_insts[bit*self.write_size]
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inst = self.driver_insts[bit * self.write_size]
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en_pin = inst.get_pin(inst.mod.en_name)
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# Determine width of wmask modified en_pin with/without col mux
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wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing)
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wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
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if (self.words_per_row == 1):
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en_gap = self.driver_spacing - en_pin.width()
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else:
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@ -184,19 +181,16 @@ class write_driver_array(design.design):
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self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
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layer=en_pin.layer,
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offset=en_pin.ll(),
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width=wmask_en_len-en_gap,
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width=wmask_en_len - en_gap,
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height=en_pin.height())
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else:
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inst = self.driver_insts[0]
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self.add_layout_pin(text=self.en_name,
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layer="m1",
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offset=inst.get_pin(inst.mod.en_name).ll().scale(0,1),
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offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1),
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width=self.width)
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def get_w_en_cin(self):
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"""Get the relative capacitance of all the enable connections in the bank"""
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#The enable is connected to a nand2 for every row.
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# The enable is connected to a nand2 for every row.
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return self.driver.get_w_en_cin() * len(self.driver_insts)
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