mirror of https://github.com/VLSIDA/OpenRAM.git
don't double count spare col
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@ -388,7 +388,8 @@ class bank(design.design):
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cols=self.num_cols + self.num_spare_cols,
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rows=self.num_rows)
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self.add_mod(self.bitcell_array)
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self.num_spare_cols += (self.bitcell_array.column_size % (self.word_size *self.words_per_row))
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if self.num_spare_cols == 0:
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self.num_spare_cols = (self.bitcell_array.column_size % (self.word_size *self.words_per_row))
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self.port_address = []
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for port in self.all_ports:
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