mirror of https://github.com/VLSIDA/OpenRAM.git
Fix well spacing issue
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@ -95,8 +95,8 @@ class bank_select(design.design):
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def calculate_module_offsets(self):
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self.xoffset_nand = self.inv4x.width + 2 * self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_nor = self.inv4x.width + 2 * self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_nand = self.inv4x.width + 3 * self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_nor = self.inv4x.width + 3 * self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_bank_sel_inv = 0
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self.xoffset_inputs = 0
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self.yoffset_maxpoint = self.num_control_lines * self.inv4x.height
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