port_data: Each submodule now specifies their bl/br names

before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

compiler/modules/port_data.py

@@ -94,8 +94,10 @@ class port_data(design.design):
         self.add_pin("rbl_bl","INOUT")
         self.add_pin("rbl_br","INOUT")
         for bit in range(self.num_cols):
-            self.add_pin("{0}_{1}".format(self.bl_names[self.port], bit),"INOUT")
-            self.add_pin("{0}_{1}".format(self.br_names[self.port], bit),"INOUT")
+            bl_name = self.precharge_array.get_bl_name(self.port)
+            br_name = self.precharge_array.get_br_name(self.port)
+            self.add_pin("{0}_{1}".format(bl_name, bit),"INOUT")
+            self.add_pin("{0}_{1}".format(br_name, bit),"INOUT")
         if self.port in self.read_ports:
             for bit in range(self.word_size):
                 self.add_pin("dout_{}".format(bit),"OUTPUT")
@@ -234,6 +236,13 @@ class port_data(design.design):
         self.precharge = factory.create(module_type="precharge",
                                         bitcell_bl = self.bl_names[0],
                                         bitcell_br = self.br_names[0])
+        # We create a dummy here to get bl/br names to add those pins to this
+        # module, which happens before we create the real precharge_array
+        self.precharge_array = factory.create(module_type="precharge_array",
+                                       columns=self.num_cols + 1,
+                                       bitcell_bl=self.bl_names[self.port],
+                                       bitcell_br=self.br_names[self.port])
+
 
 
     def create_precharge_array(self):
@@ -244,6 +253,8 @@ class port_data(design.design):
 
         self.precharge_array_inst = self.add_inst(name="precharge_array{}".format(self.port),
                                                   mod=self.precharge_array)
+        bl_name = self.precharge_array.get_bl_name(self.port)
+        br_name = self.precharge_array.get_br_name(self.port)
 
         temp = []
         # Use left BLs for RBL
@@ -251,8 +262,9 @@ class port_data(design.design):
             temp.append("rbl_bl")
             temp.append("rbl_br")
         for bit in range(self.num_cols):
-            temp.append(self.bl_names[self.port]+"_{0}".format(bit))
-            temp.append(self.br_names[self.port]+"_{0}".format(bit))
+            temp.append("{0}_{1}".format(bl_name, bit))
+            temp.append("{0}_{1}".format(br_name, bit))
+
         # Use right BLs for RBL
         if self.port==1:
             temp.append("rbl_bl")
@@ -273,15 +285,19 @@ class port_data(design.design):
         self.column_mux_array_inst = self.add_inst(name="column_mux_array{}".format(self.port),
                                                    mod=self.column_mux_array)
 
+        bl_name = self.column_mux_array.get_bl_name(self.port)
+        br_name = self.column_mux_array.get_br_name(self.port)
         temp = []
         for col in range(self.num_cols):
-            temp.append(self.bl_names[self.port]+"_{0}".format(col))
-            temp.append(self.br_names[self.port]+"_{0}".format(col))
+            temp.append("{0}_{1}".format(bl_name, col))
+            temp.append("{0}_{1}".format(br_name, col))
+
         for word in range(self.words_per_row):
             temp.append("sel_{}".format(word))
         for bit in range(self.word_size):
-            temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
-            temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
+            temp.append("{0}_out_{1}".format(bl_name, bit))
+            temp.append("{0}_out_{1}".format(br_name, bit))
+
         temp.append("gnd")
         self.connect_inst(temp)
 
@@ -299,15 +315,18 @@ class port_data(design.design):
         self.sense_amp_array_inst = self.add_inst(name="sense_amp_array{}".format(self.port),
                                                   mod=self.sense_amp_array)
 
+        bl_name = self.sense_amp_array.get_bl_name(self.port)
+        br_name = self.sense_amp_array.get_br_name(self.port)
         temp = []
         for bit in range(self.word_size):
             temp.append("dout_{}".format(bit))
             if self.words_per_row == 1:
-                temp.append(self.bl_names[self.port]+"_{0}".format(bit))
-                temp.append(self.br_names[self.port]+"_{0}".format(bit))
+                temp.append("{0}_{1}".format(bl_name, bit))
+                temp.append("{0}_{1}".format(br_name, bit))
             else:
-                temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
-                temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
+                temp.append("{0}_out_{1}".format(bl_name, bit))
+                temp.append("{0}_out_{1}".format(br_name, bit))
+
 
         temp.extend(["s_en", "vdd", "gnd"])
         self.connect_inst(temp)
@@ -322,6 +341,8 @@ class port_data(design.design):
         """ Creating Write Driver  """
         self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port),
                                                      mod=self.write_driver_array)
+        bl_name = self.write_driver_array.get_bl_name(self.port)
+        br_name = self.write_driver_array.get_br_name(self.port)
 
         temp = []
         for bit in range(self.word_size):
@@ -329,11 +350,11 @@ class port_data(design.design):
 
         for bit in range(self.word_size):
             if (self.words_per_row == 1):
-                temp.append(self.bl_names[self.port] + "_{0}".format(bit))
-                temp.append(self.br_names[self.port] + "_{0}".format(bit))
+                temp.append("{0}_{1}".format(bl_name, bit))
+                temp.append("{0}_{1}".format(br_name, bit))
             else:
-                temp.append(self.bl_names[self.port] + "_out_{0}".format(bit))
-                temp.append(self.br_names[self.port] + "_out_{0}".format(bit))
+                temp.append("{0}_out_{1}".format(bl_name, bit))
+                temp.append("{0}_out_{1}".format(br_name, bit))
 
         if self.write_size is not None:
             for i in range(self.num_wmasks):

compiler/modules/precharge_array.py

@@ -32,6 +32,21 @@ class precharge_array(design.design):
         if not OPTS.netlist_only:
             self.create_layout()
 
+    def get_bl_name(self, port=0):
+        bl_name = self.pc_cell.get_bl_names()
+        if len(self.all_ports) == 1:
+            return bl_name
+        else:
+            return bl_name + "{}".format(port)
+
+    def get_br_name(self, port=0):
+        br_name = self.pc_cell.get_br_names()
+        if len(self.all_ports) == 1:
+            return br_name
+        else:
+            return br_name + "{}".format(port)
+
+
     def add_pins(self):
         """Adds pins for spice file"""
         for i in range(self.columns):

compiler/modules/sense_amp.py

@@ -29,6 +29,12 @@ class sense_amp(design.design):
         (width, height) = (0,0)
         pin_map = []
 
+    def get_bl_names(self):
+        return "bl"
+
+    def get_br_names(self):
+        return "br"
+
     def __init__(self, name):
         design.design.__init__(self, name)
         debug.info(2, "Create sense_amp")

compiler/modules/sense_amp_array.py

@@ -34,6 +34,20 @@ class sense_amp_array(design.design):
             self.create_layout()
 
 
+    def get_bl_name(self, port=0):
+        bl_name = self.amp.get_bl_names()
+        if len(self.all_ports) == 1:
+            return bl_name
+        else:
+            return bl_name + "{}".format(port)
+
+    def get_br_name(self, port=0):
+        br_name = self.amp.get_br_names()
+        if len(self.all_ports) == 1:
+            return br_name
+        else:
+            return br_name + "{}".format(port)
+
     def create_netlist(self):
         self.add_modules()
         self.add_pins()

compiler/modules/single_level_column_mux_array.py

@@ -37,6 +37,21 @@ class single_level_column_mux_array(design.design):
         if not OPTS.netlist_only:
             self.create_layout()
 
+    def get_bl_name(self, port=0):
+        bl_name = self.mux.get_bl_names()
+        if len(self.all_ports) == 1:
+            return bl_name
+        else:
+            return bl_name + "{}".format(port)
+
+    def get_br_name(self, port=0):
+        br_name = self.mux.get_br_names()
+        if len(self.all_ports) == 1:
+            return br_name
+        else:
+            return br_name + "{}".format(port)
+
+
     def create_netlist(self):
         self.add_modules()
         self.add_pins()

compiler/modules/write_driver.py

@@ -37,6 +37,12 @@ class write_driver(design.design):
         self.pin_map = write_driver.pin_map
         self.add_pin_types(self.type_list)
 
+    def get_bl_names(self):
+        return "bl"
+
+    def get_br_names(self):
+        return "br"
+
     def get_w_en_cin(self):
         """Get the relative capacitance of a single input"""
         # This is approximated from SCMOS. It has roughly 5 3x transistor gates.

compiler/modules/write_driver_array.py

@@ -37,6 +37,19 @@ class write_driver_array(design.design):
         if not OPTS.netlist_only:
             self.create_layout()
 
+    def get_bl_name(self, port=0):
+        bl_name = self.driver.get_bl_names()
+        if len(self.all_ports) == 1:
+            return bl_name
+        else:
+            return bl_name + "{}".format(port)
+
+    def get_br_name(self, port=0):
+        br_name = self.driver.get_br_names()
+        if len(self.all_ports) == 1:
+            return br_name
+        else:
+            return br_name + "{}".format(port)
 
     def create_netlist(self):
         self.add_modules()

compiler/pgates/single_level_column_mux.py

@@ -31,6 +31,12 @@ class single_level_column_mux(pgate.pgate):
         
         pgate.pgate.__init__(self, name)
 
+    def get_bl_names(self):
+        return "bl"
+
+    def get_br_names(self):
+        return "br"
+
     def create_netlist(self):
         self.add_modules()
         self.add_pins()