mirror of https://github.com/VLSIDA/OpenRAM.git
Provide unique WL driver instance name
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@ -124,7 +124,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.wl_insts = []
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self.driver_wordline_outputs = []
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for port in self.all_ports:
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self.wl_insts.append(self.add_inst(name="wl_driver",
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self.wl_insts.append(self.add_inst(name="wl_driver{}".format(port),
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mod=self.wl_array))
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temp = []
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temp += [self.get_rbl_wordline_names(port)[port]]
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