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Don't route to clk to perimeter on m2

This commit is contained in:
mrg 2020-06-30 13:57:45 -07:00
parent a48ea52253
commit 011ac2fc05
1 changed files with 6 additions and 6 deletions
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12
compiler/modules/control_logic.py
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@ -523,12 +523,12 @@ class control_logic(design.design):
def route_clk_buf(self):
clk_pin = self.clk_buf_inst.get_pin("A")
clk_pos = clk_pin.center()
self.add_layout_pin_segment_center(text="clk",
layer="m2",
start=clk_pos,
end=clk_pos.scale(1, 0))
self.add_via_center(layers=self.m1_stack,
offset=clk_pos)
self.add_layout_pin_rect_center(text="clk",
layer="m2",
offset=clk_pos)
self.add_via_stack_center(from_layer=clk_pin.layer,
to_layer="m2",
offset=clk_pos)
self.route_output_to_bus_jogged(self.clk_buf_inst,
"clk_buf")