Variable zjog. 512 port address test. s8 port address working.

compiler/base/hierarchy_layout.py

@@ -450,26 +450,27 @@ class layout():
                     path=coordinates,
                     layer_widths=layer_widths)
 
-    def add_zjog(self, layer, start, end, first_direction="H", fixed_offset=None):
+    def add_zjog(self, layer, start, end, first_direction="H", var_offset=0.5, fixed_offset=None):
         """
         Add a simple jog at the halfway point.
         If layer is a single value, it is a path.
         If layer is a tuple, it is a wire with preferred directions.
         """
 
+        neg_offset = 1.0 - var_offset
         # vertical first
         if first_direction == "V":
             if fixed_offset:
                 mid1 = vector(start.x, fixed_offset)
             else:
-                mid1 = vector(start.x, 0.5 * start.y + 0.5 * end.y)
+                mid1 = vector(start.x, neg_offset * start.y + var_offset * end.y)
             mid2 = vector(end.x, mid1.y)
         # horizontal first
         elif first_direction == "H":
             if fixed_offset:
                 mid1 = vector(fixed_offset, start.y)
             else:
-                mid1 = vector(0.5 * start.x + 0.5 * end.x, start.y)
+                mid1 = vector(neg_offset * start.x + var_offset * end.x, start.y)
             mid2 = vector(mid1, end.y)
         else:
             debug.error("Invalid direction for jog -- must be H or V.")

compiler/modules/hierarchical_decoder.py

@@ -48,11 +48,18 @@ class hierarchical_decoder(design.design):
         self.setup_layout_constants()
         self.place_pre_decoder()
         self.place_row_decoder()
+        
+        self.height = max(self.predecoder_height, self.row_decoder_height) + self.bus_space
+        
         self.route_inputs()
         self.route_outputs()
         self.route_decoder_bus()
         self.route_vdd_gnd()
+        
         self.offset_all_coordinates()
+        
+        self.width = self.and_inst[0].rx() + self.m1_space
+        
         self.add_boundary()
         self.DRC_LVS()
                 
@@ -178,21 +185,6 @@ class hierarchical_decoder(design.design):
         # Extra bus space for supply contacts
         self.input_routing_width = self.num_inputs * self.bus_pitch + self.bus_space
 
-        # Calculates height and width of row-decoder
-        # Calculates height and width of hierarchical decoder
-        # Add extra pitch for good measure
-        self.height = max(self.predecoder_height, self.row_decoder_height) + self.bus_space
-        if (self.num_inputs == 4 or self.num_inputs == 5):
-            self.nand_width = self.and2.width
-        else:
-            self.nand_width = self.and3.width
-
-        self.width = self.input_routing_width \
-                     + self.predecoder_width \
-                     + self.internal_routing_width \
-                     + self.nand_width \
-                     + self.m1_space
-            
     def route_inputs(self):
         """ Create input bus for the predecoders """
         # Find the left-most predecoder

compiler/modules/port_address.py

@@ -93,7 +93,7 @@ class port_address(design.design):
             decoder_out_pos = decoder_out_pin.rc()
             driver_in_pin = self.wordline_driver_inst.get_pin("in_{}".format(row))
             driver_in_pos = driver_in_pin.lc()
-            self.add_zjog(self.route_layer, decoder_out_pos, driver_in_pos)
+            self.add_zjog(self.route_layer, decoder_out_pos, driver_in_pos, var_offset=0.3)
 
             self.add_via_stack_center(from_layer=decoder_out_pin.layer,
                                       to_layer=self.route_layer,

compiler/tests/18_port_address_1rw_1r_test.py

@@ -29,6 +29,10 @@ class port_address_1rw_1r_test(openram_test):
         debug.info(1, "Port address 16 rows")
         a = factory.create("port_address", cols=16, rows=16)
         self.local_check(a)
+
+        debug.info(1, "Port address 512 rows")
+        a = factory.create("port_address", cols=256, rows=512)
+        self.local_check(a)
         
         globals.end_openram()
         

compiler/tests/18_port_address_test.py

@@ -24,6 +24,10 @@ class port_address_test(openram_test):
         a = factory.create("port_address", cols=16, rows=16)
         self.local_check(a)
         
+        debug.info(1, "Port address 512 rows")
+        a = factory.create("port_address", cols=256, rows=512)
+        self.local_check(a)
+
         globals.end_openram()
         
 # run the test from the command line