mirror of https://github.com/VLSIDA/OpenRAM.git
Create RBL wordline buffer with correct polarity.
This commit is contained in:
mrg
parent
392afd4d4b
commit
c7d32089f3
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@ -63,6 +63,16 @@ class layout():
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self.translate_all(offset)
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return offset
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def offset_x_coordinates(self):
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"""
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This function is called after everything is placed to
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shift the origin to the furthest left point.
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Y offset is unchanged.
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"""
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offset = self.find_lowest_coords()
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self.translate_all(offset.scale(1, 0))
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return offset
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def get_gate_offset(self, x_offset, height, inv_num):
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"""
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Gets the base offset and y orientation of stacked rows of gates
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@ -223,10 +223,10 @@ class bank(design.design):
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# UPPER LEFT QUADRANT
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# To the left of the bitcell array above the predecoders and control logic
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x_offset = self.m2_gap + self.port_address.width
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x_offset = self.m2_gap + self.port_address[port].width
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self.port_address_offsets[port] = vector(-x_offset,
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self.main_bitcell_array_bottom)
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self.predecoder_height = self.port_address.predecoder_height + self.port_address_offsets[port].y
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self.predecoder_height = self.port_address[port].predecoder_height + self.port_address_offsets[port].y
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# LOWER LEFT QUADRANT
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# Place the col decoder left aligned with wordline driver
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@ -234,7 +234,7 @@ class bank(design.design):
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# control logic to allow control signals to easily pass over in M3
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# by placing 1 1/4 a cell pitch down because both power connections and inputs/outputs
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# may be routed in M3 or M4
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x_offset = self.central_bus_width[port] + self.port_address.wordline_driver.width
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x_offset = self.central_bus_width[port] + self.port_address[port].wordline_driver_array.width
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if self.col_addr_size > 0:
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x_offset += self.column_decoder.width + self.col_addr_bus_width
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y_offset = 1.25 * self.dff.height + self.column_decoder.height
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@ -267,7 +267,7 @@ class bank(design.design):
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# LOWER RIGHT QUADRANT
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# To the right of the bitcell array
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x_offset = self.bitcell_array_right + self.port_address.width + self.m2_gap
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x_offset = self.bitcell_array_right + self.port_address[port].width + self.m2_gap
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self.port_address_offsets[port] = vector(x_offset,
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self.main_bitcell_array_bottom)
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@ -278,7 +278,7 @@ class bank(design.design):
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# control logic to allow control signals to easily pass over in M3
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# by placing 1 1/4 a cell pitch down because both power connections and inputs/outputs
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# may be routed in M3 or M4
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x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.port_address.wordline_driver.width
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x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.port_address[port].wordline_driver_array.width
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if self.col_addr_size > 0:
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x_offset += self.column_decoder.width + self.col_addr_bus_width
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y_offset = self.bitcell_array_top + 1.25 * self.dff.height + self.column_decoder.height
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@ -366,10 +366,13 @@ class bank(design.design):
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def add_modules(self):
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""" Add all the modules using the class loader """
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self.port_address = factory.create(module_type="port_address",
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cols=self.num_cols + self.num_spare_cols,
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rows=self.num_rows)
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self.add_mod(self.port_address)
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self.port_address = []
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for port in self.all_ports:
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self.port_address.append(factory.create(module_type="port_address",
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cols=self.num_cols + self.num_spare_cols,
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rows=self.num_rows,
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port=port))
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self.add_mod(self.port_address[port])
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self.num_rbl = len(self.all_ports)
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@ -420,13 +423,10 @@ class bank(design.design):
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# gnd
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temp = self.bitcell_array.get_inouts()
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wordline_names = self.bitcell_array.get_inputs()
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# Rename the RBL WL to the enable name
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for port in self.all_ports:
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rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port]
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wordline_names = [x.replace(rbl_wl_name, "wl_en{0}".format(port)) for x in wordline_names]
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temp.extend(wordline_names)
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temp.append("rbl_wl0")
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temp.extend(self.bitcell_array.get_wordline_names())
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if len(self.all_ports) > 1:
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temp.append("rbl_wl1")
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temp.append("vdd")
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temp.append("gnd")
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@ -486,13 +486,15 @@ class bank(design.design):
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self.port_address_inst = [None] * len(self.all_ports)
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for port in self.all_ports:
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self.port_address_inst[port] = self.add_inst(name="port_address{}".format(port),
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mod=self.port_address)
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mod=self.port_address[port])
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temp = []
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for bit in range(self.row_addr_size):
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temp.append("addr{0}_{1}".format(port, bit + self.col_addr_size))
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temp.append("wl_en{}".format(port))
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temp.extend(self.bitcell_array.get_wordline_names(port))
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wordline_names = self.bitcell_array.get_wordline_names(port)
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temp.extend(wordline_names)
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temp.append("rbl_wl{}".format(port))
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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@ -852,8 +854,9 @@ class bank(design.design):
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def route_port_address_left(self, port):
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""" Connecting Wordline driver output to Bitcell WL connection """
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driver_names = ["wl_{}".format(x) for x in range(self.num_rows)]
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for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port)):
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driver_names = ["wl_{}".format(x) for x in range(self.num_rows)] + ["rbl_wl"]
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rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)[port]
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for (driver_name, array_name) in zip(driver_names, self.bitcell_array.get_wordline_names(port) + [rbl_wl_name]):
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# The mid guarantees we exit the input cell to the right.
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driver_wl_pin = self.port_address_inst[port].get_pin(driver_name)
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driver_wl_pos = driver_wl_pin.rc()
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@ -1021,10 +1024,6 @@ class bank(design.design):
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connection.append((self.prefix + "p_en_bar{}".format(port),
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self.port_data_inst[port].get_pin("p_en_bar")))
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rbl_wl_name = self.bitcell_array.get_rbl_wordline_names(port)
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connection.append((self.prefix + "wl_en{}".format(port),
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self.bitcell_array_inst.get_pin(rbl_wl_name[port])))
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if port in self.write_ports:
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connection.append((self.prefix + "w_en{}".format(port),
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self.port_data_inst[port].get_pin("w_en")))
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@ -1045,7 +1044,7 @@ class bank(design.design):
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self.add_via_stack_center(from_layer=pin.layer,
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to_layer="m2",
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offset=control_pos)
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# clk to wordline_driver
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control_signal = self.prefix + "wl_en{}".format(port)
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if port % 2:
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@ -54,6 +54,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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""" Add the modules used in this design """
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self.local_mods = []
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# Special case of a single local array
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# so it should contain the left and possibly right RBL
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if len(self.column_sizes) == 1:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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@ -66,19 +68,21 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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return
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for i, cols in enumerate(self.column_sizes):
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# Always add the left RBLs to the first subarray and the right RBLs to the last subarray
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# Always add the left RBLs to the first subarray
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if i == 0:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=cols,
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rbl=self.rbl,
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left_rbl=[0])
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# Add the right RBL to the last subarray
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elif i == len(self.column_sizes) - 1 and len(self.all_ports) > 1:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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cols=cols,
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rbl=self.rbl,
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right_rbl=[1])
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# Middle subarrays do not have any RBLs
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else:
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la = factory.create(module_type="local_bitcell_array",
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rows=self.row_size,
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@ -55,9 +55,9 @@ class hierarchical_decoder(design.design):
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self.route_decoder_bus()
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self.route_vdd_gnd()
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self.offset_all_coordinates()
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self.offset_x_coordinates()
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self.width = self.and_inst[0].rx() + self.m1_space
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self.width = self.and_inst[0].rx() + 0.5 * self.m1_width
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self.add_boundary()
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self.DRC_LVS()
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@ -17,10 +17,11 @@ class port_address(design.design):
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Create the address port (row decoder and wordline driver)..
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"""
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def __init__(self, cols, rows, name=""):
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def __init__(self, cols, rows, port, name=""):
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self.num_cols = cols
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self.num_rows = rows
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self.port = port
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self.addr_size = ceil(log(self.num_rows, 2))
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if name == "":
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@ -39,6 +40,7 @@ class port_address(design.design):
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self.add_modules()
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self.create_row_decoder()
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self.create_wordline_driver()
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self.create_rbl_driver()
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def create_layout(self):
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if "li" in layer:
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@ -59,6 +61,8 @@ class port_address(design.design):
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for bit in range(self.num_rows):
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self.add_pin("wl_{0}".format(bit), "OUTPUT")
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self.add_pin("rbl_wl", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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@ -71,10 +75,12 @@ class port_address(design.design):
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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for inst in self.insts:
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for inst in [self.wordline_driver_array_inst, self.row_decoder_inst]:
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self.copy_power_pins(inst, "vdd")
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self.copy_power_pins(inst, "gnd")
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self.copy_power_pins(self.rbl_driver_inst, "vdd")
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def route_pins(self):
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for row in range(self.addr_size):
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decoder_name = "addr_{}".format(row)
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@ -82,16 +88,16 @@ class port_address(design.design):
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for row in range(self.num_rows):
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driver_name = "wl_{}".format(row)
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self.copy_layout_pin(self.wordline_driver_inst, driver_name)
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self.copy_layout_pin(self.wordline_driver_array_inst, driver_name)
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self.copy_layout_pin(self.wordline_driver_inst, "en", "wl_en")
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self.copy_layout_pin(self.rbl_driver_inst, "Z", "rbl_wl")
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def route_internal(self):
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for row in range(self.num_rows):
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# The pre/post is to access the pin from "outside" the cell to avoid DRCs
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decoder_out_pin = self.row_decoder_inst.get_pin("decode_{}".format(row))
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decoder_out_pos = decoder_out_pin.rc()
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driver_in_pin = self.wordline_driver_inst.get_pin("in_{}".format(row))
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driver_in_pin = self.wordline_driver_array_inst.get_pin("in_{}".format(row))
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driver_in_pos = driver_in_pin.lc()
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self.add_zjog(self.route_layer, decoder_out_pos, driver_in_pos, var_offset=0.3)
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@ -102,6 +108,20 @@ class port_address(design.design):
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self.add_via_stack_center(from_layer=driver_in_pin.layer,
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to_layer=self.route_layer,
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offset=driver_in_pos)
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# Route the RBL from the enable input
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en_pin = self.wordline_driver_array_inst.get_pin("en")
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rbl_in_pin = self.rbl_driver_inst.get_pin("A")
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rbl_in_pos = rbl_in_pin.center()
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mid_pos = vector(en_pin.cx(), rbl_in_pin.cy())
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self.add_path(rbl_in_pin.layer, [rbl_in_pos, mid_pos])
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self.add_via_stack_center(from_layer=rbl_in_pin.layer,
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to_layer=en_pin.layer,
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offset=mid_pos)
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self.add_layout_pin_segment_center(text="wl_en",
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layer=en_pin.layer,
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start=mid_pos,
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end=en_pin.center())
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def add_modules(self):
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@ -109,10 +129,33 @@ class port_address(design.design):
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num_outputs=self.num_rows)
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self.add_mod(self.row_decoder)
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self.wordline_driver = factory.create(module_type="wordline_driver_array",
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rows=self.num_rows,
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cols=self.num_cols)
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self.add_mod(self.wordline_driver)
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self.wordline_driver_array = factory.create(module_type="wordline_driver_array",
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rows=self.num_rows,
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cols=self.num_cols)
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self.add_mod(self.wordline_driver_array)
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try:
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local_array_size = OPTS.local_array_size
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driver_size = int(self.num_cols / local_array_size)
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except AttributeError:
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local_array_size = 0
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# Defautl to FO4
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driver_size = int(self.num_cols / 4)
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# The polarity must be switched if we have a hierarchical wordline
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# to compensate for the local array inverters
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b = factory.create(module_type="bitcell")
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if local_array_size > 0:
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self.rbl_driver = factory.create(module_type="inv_dec",
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size=driver_size,
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height=b.height)
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else:
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self.rbl_driver = factory.create(module_type="buf_dec",
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size=driver_size,
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height=b.height)
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self.add_mod(self.rbl_driver)
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def create_row_decoder(self):
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""" Create the hierarchical row decoder """
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@ -128,11 +171,24 @@ class port_address(design.design):
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def create_rbl_driver(self):
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""" Create the RBL Wordline Driver """
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self.rbl_driver_inst = self.add_inst(name="rbl_driver",
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mod=self.rbl_driver)
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temp = []
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temp.append("wl_en")
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temp.append("rbl_wl")
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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def create_wordline_driver(self):
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""" Create the Wordline Driver """
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self.wordline_driver_inst = self.add_inst(name="wordline_driver",
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mod=self.wordline_driver)
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self.wordline_driver_array_inst = self.add_inst(name="wordline_driver",
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mod=self.wordline_driver_array)
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temp = []
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for row in range(self.num_rows):
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@ -150,11 +206,23 @@ class port_address(design.design):
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"""
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row_decoder_offset = vector(0, 0)
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wordline_driver_offset = vector(self.row_decoder.width, 0)
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self.wordline_driver_inst.place(wordline_driver_offset)
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self.row_decoder_inst.place(row_decoder_offset)
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wordline_driver_array_offset = vector(self.row_decoder_inst.rx(), 0)
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self.wordline_driver_array_inst.place(wordline_driver_array_offset)
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x_offset = self.wordline_driver_array_inst.rx() - self.rbl_driver.width - self.m1_pitch
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if self.port == 0:
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rbl_driver_offset = vector(x_offset,
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0)
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self.rbl_driver_inst.place(rbl_driver_offset, "MX")
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else:
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rbl_driver_offset = vector(x_offset,
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self.wordline_driver_array.height)
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self.rbl_driver_inst.place(rbl_driver_offset)
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# Pass this up
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self.predecoder_height = self.row_decoder.predecoder_height
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self.height = self.row_decoder.height
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self.width = self.wordline_driver_inst.rx()
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self.width = self.wordline_driver_array_inst.rx()
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@ -109,12 +109,13 @@ class wordline_buffer_array(design.design):
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def place_drivers(self):
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for row in range(self.rows):
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# These are flipped since we always start with an RBL on the bottom
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if (row % 2):
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y_offset = self.wl_driver.height * (row + 1)
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inst_mirror = "MX"
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else:
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y_offset = self.wl_driver.height * row
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inst_mirror = "R0"
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else:
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y_offset = self.wl_driver.height * (row + 1)
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inst_mirror = "MX"
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offset = [0, y_offset]
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@ -44,7 +44,7 @@ class wordline_driver_array(design.design):
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self.place_drivers()
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self.route_layout()
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self.route_vdd_gnd()
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self.offset_all_coordinates()
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self.offset_x_coordinates()
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self.add_boundary()
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self.DRC_LVS()
|
||||
|
||||
|
|
@ -60,8 +60,10 @@ class wordline_driver_array(design.design):
|
|||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_modules(self):
|
||||
|
||||
self.wl_driver = factory.create(module_type="wordline_driver",
|
||||
size=self.cols)
|
||||
cols=self.cols)
|
||||
|
||||
self.add_mod(self.wl_driver)
|
||||
|
||||
def route_vdd_gnd(self):
|
||||
|
|
|
|||
|
|
@ -139,6 +139,7 @@ class options(optparse.Values):
|
|||
bank_select = "bank_select"
|
||||
bitcell_array = "bitcell_array"
|
||||
bitcell = "bitcell"
|
||||
buf_dec = "pbuf"
|
||||
column_mux_array = "single_level_column_mux_array"
|
||||
control_logic = "control_logic"
|
||||
decoder = "hierarchical_decoder"
|
||||
|
|
|
|||
|
|
@ -96,4 +96,4 @@ class pbuf(pgate.pgate):
|
|||
offset=a_pin.center(),
|
||||
width=a_pin.width(),
|
||||
height=a_pin.height())
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -18,9 +18,9 @@ class wordline_driver(design.design):
|
|||
This is an AND (or NAND) with configurable drive strength to drive the wordlines.
|
||||
It is matched to the bitcell height.
|
||||
"""
|
||||
def __init__(self, name, size=1, height=None):
|
||||
def __init__(self, name, cols=1, height=None):
|
||||
debug.info(1, "Creating wordline_driver {}".format(name))
|
||||
self.add_comment("size: {}".format(size))
|
||||
self.add_comment("cols: {}".format(cols))
|
||||
super().__init__(name)
|
||||
|
||||
if height is None:
|
||||
|
|
@ -28,7 +28,7 @@ class wordline_driver(design.design):
|
|||
self.height = b.height
|
||||
else:
|
||||
self.height = height
|
||||
self.size = size
|
||||
self.cols = cols
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
|
|
@ -42,10 +42,25 @@ class wordline_driver(design.design):
|
|||
def create_modules(self):
|
||||
self.nand = factory.create(module_type="nand2_dec",
|
||||
height=self.height)
|
||||
|
||||
self.driver = factory.create(module_type="inv_dec",
|
||||
size=self.size,
|
||||
height=self.nand.height)
|
||||
|
||||
try:
|
||||
local_array_size = OPTS.local_array_size
|
||||
driver_size = int(self.cols / local_array_size)
|
||||
except AttributeError:
|
||||
local_array_size = 0
|
||||
# Defautl to FO4
|
||||
driver_size = int(self.cols / 4)
|
||||
|
||||
# The polarity must be switched if we have a hierarchical wordline
|
||||
# to compensate for the local array inverters
|
||||
if local_array_size > 0:
|
||||
self.driver = factory.create(module_type="buf_dec",
|
||||
size=driver_size,
|
||||
height=self.nand.height)
|
||||
else:
|
||||
self.driver = factory.create(module_type="inv_dec",
|
||||
size=driver_size,
|
||||
height=self.nand.height)
|
||||
|
||||
self.add_mod(self.nand)
|
||||
self.add_mod(self.driver)
|
||||
|
|
|
|||
Loading…
Reference in New Issue