mirror of https://github.com/VLSIDA/OpenRAM.git
Replica bitcell with all the fixings
This commit is contained in:
mrg
parent
eef97ff215
commit
8e890c2014
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@ -392,7 +392,7 @@ class bank(design.design):
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def create_bitcell_array(self):
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""" Creating Bitcell Array """
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import pdb; pdb.set_trace()
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self.bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
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mod=self.bitcell_array)
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@ -5,22 +5,22 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import bitcell_base_array
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from globals import OPTS
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from sram_factory import factory
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from vector import vector
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import debug
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class local_bitcell_array(design.design):
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class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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"""
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A local bitcell array is a bitcell array with a wordline driver.
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This can either be a single aray on its own if there is no hierarchical WL
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or it can be combined into a larger array with hierarchical WL.
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"""
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def __init__(self, rows, cols, ports, left_rbl=0, right_rbl=0, name=""):
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design.design.__init__(self, name)
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debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,
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self.num_words))
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def __init__(self, rows, cols, ports, left_rbl=0, right_rbl=0, add_replica=True, name=""):
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super().__init__(name, rows, cols, 0)
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debug.info(2, "create local array of size {} rows x {} cols words".format(rows,
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cols + left_rbl + right_rbl))
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self.rows = rows
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self.cols = cols
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@ -66,16 +66,47 @@ class local_bitcell_array(design.design):
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self.add_mod(self.bitcell_array)
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self.wl_array = factory.create(module_type="wordline_buffer_array",
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rows=self.rows,
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rows=self.rows + len(self.all_ports),
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cols=self.cols)
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self.add_mod(self.wl_array)
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def add_pins(self):
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self.bitline_names = self.bitcell_array.get_all_bitline_names()
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self.add_pin_list(self.bitline_names, "INOUT")
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self.wordline_names = self.bitcell_array.get_all_wordline_names()
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self.add_pin_list(self.wordline_names, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.wl_inst = self.add_inst(mod=self.wl_array)
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self.connect_inst(self.pins)
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internal_wl_names = [x + "i" for x in self.wordline_names]
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self.wl_inst = self.add_inst(name="wl_driver",
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mod=self.wl_array)
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self.connect_inst(self.wordline_names + internal_wl_names + ["vdd", "gnd"])
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self.array_inst = self.add_inst(mod=self.bitcell_array,
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self.array_inst = self.add_inst(name="array",
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mod=self.bitcell_array,
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offset=self.wl_inst.lr())
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self.connect_inst(self.pins)
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self.connect_inst(self.bitline_names + internal_wl_names + ["vdd", "gnd"])
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def place(self):
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""" Place the bitcelll array to the right of the wl driver. """
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self.wl_inst.place(vector(0, 0))
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self.array_inst.place(self.wl_inst.lr())
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self.height = self.bitcell_array.height
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self.width = self.array_inst.rx()
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def add_layout_pins(self):
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for (x, y) in zip(self.bitline_names, self.bitcell_array.get_inouts()):
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self.copy_layout_pin(self.array_inst, y, x)
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for (x, y) in zip(self.wordline_names, self.wl_array.get_inputs()):
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self.copy_layout_pin(self.wl_inst, y, x)
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@ -42,9 +42,9 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.add_left_rbl = 0
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self.add_right_rbl = 0
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debug.check(left_rbl + right_rbl == len(self.all_ports),
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debug.check(left_rbl + right_rbl <= len(self.all_ports),
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"Invalid number of RBLs for port configuration.")
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debug.check(left_rbl + right_rbl == len(self.bitcell_ports),
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debug.check(left_rbl + right_rbl <= len(self.bitcell_ports),
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"Bitcell ports must match total RBLs.")
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# Two dummy rows plus replica even if we don't add the column
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@ -134,27 +134,26 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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end_caps_enabled = False
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# Dummy Row or Col Cap, depending on bitcell array properties
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edge_row_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
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self.edge_row = factory.create(module_type=edge_row_module_type,
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col_cap_module_type = ("col_cap_array" if end_caps_enabled else "dummy_array")
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self.col_cap = factory.create(module_type=col_cap_module_type,
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cols=self.column_size,
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rows=1,
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# dummy column + left replica column(s)
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column_offset=1 + self.add_left_rbl,
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mirror=0)
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self.add_mod(self.edge_row)
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self.add_mod(self.col_cap)
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# Dummy Col or Row Cap, depending on bitcell array properties
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edge_col_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array")
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row_cap_module_type = ("row_cap_array" if end_caps_enabled else "dummy_array")
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self.edge_col_left = factory.create(module_type=edge_col_module_type,
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self.row_cap_left = factory.create(module_type=row_cap_module_type,
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cols=1,
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column_offset=0,
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl + 1) % 2)
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self.add_mod(self.edge_col_left)
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self.add_mod(self.row_cap_left)
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self.edge_col_right = factory.create(module_type=edge_col_module_type,
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self.row_cap_right = factory.create(module_type=row_cap_module_type,
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cols=1,
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# dummy column
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# + left replica column(s)
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@ -163,100 +162,111 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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column_offset = 1 + self.add_left_rbl + self.column_size + self.add_right_rbl,
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl + 1) %2)
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self.add_mod(self.edge_col_right)
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self.add_mod(self.row_cap_right)
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def add_pins(self):
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self.bitcell_array_wl_names = self.bitcell_array.get_all_wordline_names()
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self.bitcell_array_bl_names = self.bitcell_array.get_all_bitline_names()
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self.add_bitline_pins()
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self.add_wordline_pins()
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_bitline_pins(self):
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# All bitline names for all ports
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self.bitline_names = []
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# Bitline names for each port
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self.bitline_names_by_port = [[] for x in self.all_ports]
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# Replica wordlines by port
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self.replica_bitline_names = [[] for x in self.all_ports]
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# Replica wordlines by port (bl only)
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self.replica_bl_names = [[] for x in self.all_ports]
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# Dummy wordlines by port
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self.dummy_bitline_names = []
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# Regular array bitline names
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self.bitcell_array_bitline_names = self.bitcell_array.get_all_bitline_names()
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# These are the non-indexed names
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self.dummy_cell_wl_names = ["dummy_" + x for x in self.cell.get_all_wl_names()]
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self.dummy_cell_bl_names = ["dummy_" + x for x in self.cell.get_all_bitline_names()]
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self.dummy_row_bl_names = self.bitcell_array_bl_names
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dummy_bitline_names = ["dummy_" + x for x in self.cell.get_all_bitline_names()]
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self.dummy_bitline_names.append([x+"_left" for x in dummy_bitline_names])
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self.dummy_bitline_names.append([x+"_right" for x in dummy_bitline_names])
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# A dictionary because some ports may have nothing
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self.rbl_bl_names = {}
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self.rbl_br_names = {}
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self.rbl_wl_names = {}
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# Create the full WL names include dummy, replica, and regular bit cells
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self.replica_col_wl_names = []
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self.replica_col_wl_names.extend(["{0}_bot".format(x) for x in self.dummy_cell_wl_names])
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# Left port WLs (one dummy for each port when we allow >1 port)
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for port in range(self.add_left_rbl):
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# Make names for all RBLs
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wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x), port) for x in range(len(self.cell.get_all_wl_names()))]
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# Keep track of the pin that is the RBL
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self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
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self.replica_col_wl_names.extend(wl_names)
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# Regular WLs
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self.replica_col_wl_names.extend(self.bitcell_array_wl_names)
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# Right port WLs (one dummy for each port when we allow >1 port)
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for port in range(self.add_left_rbl, self.add_left_rbl + self.add_right_rbl):
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# Make names for all RBLs
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wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x), port) for x in range(len(self.cell.get_all_wl_names()))]
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# Keep track of the pin that is the RBL
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self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
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self.replica_col_wl_names.extend(wl_names)
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self.replica_col_wl_names.extend(["{0}_top".format(x) for x in self.dummy_cell_wl_names])
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# Create the full WL names include dummy, replica, and regular bit cells
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# Left/right dummy columns are connected identically to the replica column
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self.dummy_col_wl_names = []
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self.dummy_col_wl_names.extend(["{0}_bot".format(x) for x in self.dummy_cell_wl_names])
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# Left port WLs (one dummy for each port when we allow >1 port)
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for port in range(self.left_rbl):
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# Make names for all RBLs
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wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x), port) for x in range(len(self.cell.get_all_wl_names()))]
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# Keep track of the pin that is the RBL
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self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
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self.dummy_col_wl_names.extend(wl_names)
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# Regular WLs
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self.dummy_col_wl_names.extend(self.bitcell_array_wl_names)
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# Right port WLs (one dummy for each port when we allow >1 port)
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for port in range(self.left_rbl, self.left_rbl + self.right_rbl):
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# Make names for all RBLs
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wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x), port) for x in range(len(self.cell.get_all_wl_names()))]
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# Keep track of the pin that is the RBL
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self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
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self.dummy_col_wl_names.extend(wl_names)
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self.dummy_col_wl_names.extend(["{0}_top".format(x) for x in self.dummy_cell_wl_names])
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# Per port bitline names
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self.replica_bl_names = {}
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self.replica_wl_names = {}
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# Array of all port bitline names
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for port in range(self.add_left_rbl + self.add_right_rbl):
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left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))]
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right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))]
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# Keep track of the left pins that are the RBL
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self.rbl_bl_names[port]=left_names[self.bitcell_ports[port]]
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self.rbl_br_names[port]=right_names[self.bitcell_ports[port]]
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self.replica_bl_names[port]=left_names[self.bitcell_ports[port]]
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# Interleave the left and right lists
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bl_names = [x for t in zip(left_names, right_names) for x in t]
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self.replica_bl_names[port] = bl_names
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bitline_names = [x for t in zip(left_names, right_names) for x in t]
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self.replica_bitline_names[port] = bitline_names
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# Dummy bitlines are not connected to anything
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# br pins are not connected to anything
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for port in range(self.add_left_rbl):
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self.bitline_names.extend(self.replica_bitline_names[port])
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self.bitline_names.extend(self.bitcell_array_bitline_names)
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# br pins are not connected to anything
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for port in range(self.left_rbl, self.left_rbl + self.right_rbl):
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self.bitline_names.extend(self.replica_bitline_names[port])
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self.add_pin_list(self.bitline_names, "INOUT")
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def add_wordline_pins(self):
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# All wordline names for all ports
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self.wordline_names = []
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# Wordline names for each port
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self.wordline_names_by_port = [[] for x in self.all_ports]
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# Replica wordlines by port
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self.replica_wordline_names = [[] for x in self.all_ports]
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# Dummy wordlines
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self.dummy_wordline_names = {}
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# Regular array wordline names
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self.bitcell_array_wordline_names = self.bitcell_array.get_all_wordline_names()
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# These are the non-indexed names
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dummy_cell_wl_names = ["dummy_" + x for x in self.cell.get_all_wl_names()]
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# Create the full WL names include dummy, replica, and regular bit cells
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self.wordline_names = []
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self.dummy_wordline_names["bot"] = ["{0}_bot".format(x) for x in dummy_cell_wl_names]
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self.wordline_names.extend(self.dummy_wordline_names["bot"])
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# Left port WLs
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for port in range(self.left_rbl):
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# Make names for all RBLs
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wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x), port) for x in range(len(self.cell.get_all_wl_names()))]
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# Keep track of the pin that is the RBL
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self.replica_wordline_names[port] = wl_names
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self.wordline_names.extend(wl_names)
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# Regular WLs
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self.wordline_names.extend(self.bitcell_array_wordline_names)
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# Right port WLs
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for port in range(self.left_rbl, self.left_rbl + self.right_rbl):
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# Make names for all RBLs
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wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x), port) for x in range(len(self.cell.get_all_wl_names()))]
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# Keep track of the pin that is the RBL
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self.replica_wordline_names[port] = wl_names
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self.wordline_names.extend(wl_names)
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self.dummy_wordline_names["top"] = ["{0}_top".format(x) for x in dummy_cell_wl_names]
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self.wordline_names.extend(self.dummy_wordline_names["top"])
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# Array of all port wl names
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for port in range(self.left_rbl + self.right_rbl):
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wl_names = ["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()]
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self.replica_wl_names[port] = wl_names
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# External pins
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self.add_pin_list(self.bitcell_array_bl_names, "INOUT")
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# Need to sort by port order since dictionary values may not be in order
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bl_names = [self.rbl_bl_names[x] for x in sorted(self.rbl_bl_names.keys())]
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br_names = [self.rbl_br_names[x] for x in sorted(self.rbl_br_names.keys())]
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for (bl_name, br_name) in zip(bl_names, br_names):
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self.add_pin(bl_name, "OUTPUT")
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self.add_pin(br_name, "OUTPUT")
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self.add_pin_list(self.bitcell_array_wl_names, "INPUT")
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# Need to sort by port order since dictionary values may not be in order
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wl_names = [self.rbl_wl_names[x] for x in sorted(self.rbl_wl_names.keys())]
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for pin_name in wl_names:
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self.add_pin(pin_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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self.replica_wordline_names[port] = wl_names
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self.add_pin_list(self.wordline_names, "INPUT")
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def create_instances(self):
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""" Create the module instances used in this design """
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@ -268,14 +278,14 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.bitcell_array_bl_names + self.bitcell_array_wl_names + supplies)
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self.connect_inst(self.bitcell_array_bitline_names + self.bitcell_array_wordline_names + supplies)
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# Replica columns
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self.replica_col_inst = {}
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for port in range(self.add_left_rbl + self.add_right_rbl):
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self.replica_col_inst[port]=self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port])
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self.connect_inst(self.replica_bl_names[port] + self.replica_col_wl_names + supplies)
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self.connect_inst(self.replica_bitline_names[port] + self.wordline_names + supplies)
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_inst = {}
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@ -283,23 +293,27 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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for port in range(self.left_rbl + self.right_rbl):
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self.dummy_row_replica_inst[port]=self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + self.replica_wl_names[port] + supplies)
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self.connect_inst(self.bitcell_array_bitline_names + self.replica_wordline_names[port] + supplies)
|
||||
|
||||
# Top/bottom dummy rows or col caps
|
||||
self.dummy_row_bot_inst=self.add_inst(name="dummy_row_bot",
|
||||
mod=self.edge_row)
|
||||
self.connect_inst(self.dummy_row_bl_names + [x + "_bot" for x in self.dummy_cell_wl_names] + supplies)
|
||||
mod=self.col_cap)
|
||||
self.connect_inst(self.bitcell_array_bitline_names
|
||||
+ self.dummy_wordline_names["bot"]
|
||||
+ supplies)
|
||||
self.dummy_row_top_inst=self.add_inst(name="dummy_row_top",
|
||||
mod=self.edge_row)
|
||||
self.connect_inst(self.dummy_row_bl_names + [x + "_top" for x in self.dummy_cell_wl_names] + supplies)
|
||||
mod=self.col_cap)
|
||||
self.connect_inst(self.bitcell_array_bitline_names
|
||||
+ self.dummy_wordline_names["top"]
|
||||
+ supplies)
|
||||
|
||||
# Left/right Dummy columns
|
||||
self.dummy_col_left_inst=self.add_inst(name="dummy_col_left",
|
||||
mod=self.edge_col_left)
|
||||
self.connect_inst([x + "_left" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies)
|
||||
mod=self.row_cap_left)
|
||||
self.connect_inst(self.dummy_bitline_names[0] + self.wordline_names + supplies)
|
||||
self.dummy_col_right_inst=self.add_inst(name="dummy_col_right",
|
||||
mod=self.edge_col_right)
|
||||
self.connect_inst([x + "_right" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies)
|
||||
mod=self.row_cap_right)
|
||||
self.connect_inst(self.dummy_bitline_names[-1] + self.wordline_names + supplies)
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
|
|
@ -372,19 +386,20 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
|||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
|
||||
# All wordlines
|
||||
# Main array wl and bl/br
|
||||
pin_names = self.bitcell_array.get_pin_names()
|
||||
for pin_name in pin_names:
|
||||
for wl in self.bitcell_array_wl_names:
|
||||
for wl in self.bitcell_array_wordline_names:
|
||||
if wl in pin_name:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
for bitline in self.bitcell_array_bl_names:
|
||||
for bitline in self.bitcell_array_bitline_names:
|
||||
if bitline in pin_name:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
|
|
@ -394,32 +409,35 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
|||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
# Replica wordlines
|
||||
for port in range(self.add_left_rbl + self.add_right_rbl):
|
||||
inst = self.replica_col_inst[port]
|
||||
for (pin_name, wl_name) in zip(self.cell.get_all_wl_names(), self.replica_wl_names[port]):
|
||||
# +1 for dummy row
|
||||
pin_bit = port + 1
|
||||
# +row_size if above the array
|
||||
if port>=self.add_left_rbl:
|
||||
pin_bit += self.row_size
|
||||
# Dummy wordlines
|
||||
for (name, inst) in [("bot", self.dummy_row_bot_inst), ("top", self.dummy_row_top_inst)]:
|
||||
for (pin_name, wl_name) in zip(self.cell.get_all_wl_names(), self.dummy_wordline_names[name]):
|
||||
# It's always a single row
|
||||
pin = inst.get_pin(pin_name + "_0")
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
# Replica wordlines (go by the row instead of replica column because we may have to add a pin
|
||||
# even though the column is in another local bitcell array)
|
||||
for (port, inst) in list(self.dummy_row_replica_inst.items()):
|
||||
for (pin_name, wl_name) in zip(self.cell.get_all_wl_names(), self.replica_wordline_names[port]):
|
||||
pin = inst.get_pin(pin_name + "_0")
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
pin_name += "_{}".format(pin_bit)
|
||||
pin = inst.get_pin(pin_name)
|
||||
if wl_name in self.rbl_wl_names.values():
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
# Replica bitlines
|
||||
for port in range(self.add_left_rbl + self.add_right_rbl):
|
||||
inst = self.replica_col_inst[port]
|
||||
for (pin_name, bl_name) in zip(self.cell.get_all_bitline_names(), self.replica_bl_names[port]):
|
||||
for (pin_name, bl_name) in zip(self.cell.get_all_bitline_names(), self.replica_bitline_names[port]):
|
||||
pin = inst.get_pin(pin_name)
|
||||
|
||||
if bl_name in self.rbl_bl_names or bl_name in self.rbl_br_names:
|
||||
if bl_name in self.replica_bl_names:
|
||||
name = bl_name
|
||||
else:
|
||||
name = "rbl_{0}_{1}".format(pin_name, port)
|
||||
|
|
@ -441,22 +459,17 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
|||
loc=pin.center(),
|
||||
directions=("V", "V"),
|
||||
start_layer=pin.layer)
|
||||
|
||||
|
||||
for inst in list(self.replica_col_inst.values()):
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
|
||||
def get_rbl_wl_name(self, port):
|
||||
""" Return the WL for the given RBL port """
|
||||
return self.rbl_wl_names[port]
|
||||
return self.replica_wordline_names[port]
|
||||
|
||||
def get_rbl_bl_name(self, port):
|
||||
""" Return the BL for the given RBL port """
|
||||
return self.rbl_bl_names[port]
|
||||
|
||||
def get_rbl_br_name(self, port):
|
||||
""" Return the BR for the given RBL port """
|
||||
return self.rbl_br_names[port]
|
||||
return self.replica_bl_names[port]
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Power of Bitcell array and bitline in nW."""
|
||||
|
|
|
|||
|
|
@ -188,8 +188,6 @@ class replica_column(design.design):
|
|||
for pin_name in ["vdd", "gnd"]:
|
||||
if inst in [self.cell_inst[0], self.cell_inst[self.total_size - 1]]:
|
||||
self.copy_power_pins(inst, pin_name)
|
||||
else:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
|
||||
def get_bitcell_pins(self, row, col):
|
||||
""" Creates a list of connections in the bitcell,
|
||||
|
|
|
|||
|
|
@ -58,8 +58,11 @@ class wordline_buffer_array(design.design):
|
|||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_modules(self):
|
||||
b = factory.create(module_type="bitcell")
|
||||
|
||||
self.wl_driver = factory.create(module_type="inv_dec",
|
||||
size=self.cols)
|
||||
size=self.cols,
|
||||
height=b.height)
|
||||
self.add_mod(self.wl_driver)
|
||||
|
||||
def route_vdd_gnd(self):
|
||||
|
|
|
|||
|
|
@ -22,10 +22,14 @@ class local_bitcell_array_test(openram_test):
|
|||
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell")
|
||||
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4)
|
||||
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica")
|
||||
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, ports=[0], add_replica=False)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
|
||||
a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0])
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue